为什么 Verilog 不被认为是一种编程语言? [英] Why is Verilog not considered a programming language?
本文介绍了为什么 Verilog 不被认为是一种编程语言?的处理方法，对大家解决问题具有一定的参考价值，需要的朋友们下面随着小编来一起学习吧！
问题描述
在课堂上教授说学生不应该说他们学会了用 Verilog 编程.他说像 Verilog 这样的东西不是用来编程的，而是用来设计的.那么 Verilog 与其他编程语言有何不同?
In class the professor said that students shouldn't say that they learned to program in Verilog. He said something like Verilog isn't used to program it's used to design. So how is Verilog different from other programming languages?
推荐答案
Verilog 是一种硬件定义语言.编程语言通常被理解为告诉现有硬件要做什么的语言，而不是重新配置所述硬件的语言.
Verilog is a hardware definition language. Programming languages are generally understood to be languages for telling existing hardware what to do, not for reconfiguring said hardware.
这篇关于为什么 Verilog 不被认为是一种编程语言?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
查看全文
