如何模拟“add eax, 1"在序言中? [英] How to simulate "add eax, 1" in Prolog?

问题描述

我正在尝试使用 Prolog 模拟一些简单的 asm 代码.(32 位)

I am trying to simulate some simple asm code using Prolog. (32 bit)

我是 Prolog 的新手，我遇到了一些问题而没有任何解决方案.

I am new in Prolog and I am stucked in some problems without any solutions.

基本上如果这里是代码:

Basically if here is the code:

...
add eax, 1
...

我想以这种方式模拟:

...
EAX is EAX - 1,
...

和 swipl 会产生如下错误:

and swipl will generate errors like :

  Call: (7) 1 is 1-1 ? creep
 Fail: (7) 1 is 1-1 ? creep
 ....
 false

我知道基本上我可以这样做:

I know basically I could do like this:

EAX_temp is EAX + 1 

但是我怎样才能在接下来的指令中继续操作 EAX ......?

But how can I keep manipulate EAX in next instructions..?

谁能给我一些帮助..?谢谢！

Could any one give me some help..? Thank you!

推荐答案

可能有几种好方法可以做到这一点.答案可能会根据您目前尚不清楚的上下文进一步完善.

There are probably several good ways to do this. And the answer might further be refined by your context which is currently not clear.

一种方法，您可以为寄存器值创建动态事实:

One way, is you could create dynamic facts for register values:

:- dynamic(register/2).  % Fill in as needed

register(eax, 0).
register(ebx, 0).
...

add(Reg, Value) :-
    (   retract(register(Reg, OldValue))
    ->  NewValue is OldValue + Value
    ;   NewValue = Value                % If the register wasn't defined
    ),
    assertz(register(Reg, NewValue)).

然后做:

add(eax, 4).           % add eax,4

要读取寄存器，您只需使用，例如:

To read a register, you would just use, for example:

register(eax, EAXValue).

assert 和 retract 的主要缺点是它们比列表操作花费更多的 CPU 时间.但我认为它们对于此类应用程序有意义，在这种应用程序中，您有一个由多个寄存器值表示的 CPU状态".

The main drawback of assert and retract is that they take a lot more CPU time than list manipulation. But I think they make sense for this kind of application where you have a CPU "state" that is represented by several register values.

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