SystemVerilog 结构体的单个变量可以用 ++ 递增吗? [英] Can the indivdual variables of a SystemVerilog struct be incremented with ++?

问题描述

我已经定义了一个包含三个整数的结构，然后创建了该结构的动态数组.在代码的后面，我想增加结构中的一些整数值:

I have defined a structure with three integers, then created a dynamic array of the structure. Later in the code, I want to increment some of the integer values in the structure:

typedef struct {
  integer tc;
  integer pass;
  integer fail;
} score_t; 

score_t    scorecard[]; 
integer    tc_count;

initial
....
scorecard = new[`MAX_TC]; 
....
scorecard[tc_count].fail  = 0;
....
scorecard[tc_count].fail++;

但是，当我在 Aldec Active-HDL 中编译时，出现以下错误:

However, when I compile in Aldec Active-HDL I get the following error:

Error: VCP2615 ../../../m3_test_load_tb.sv : (283, 33): 
                    scorecard[tc_count].fail is not l-value.

这是语言的限制吗?我可以分配给一个临时变量来执行增量操作，然后将值放回结构中，但这似乎很笨拙.

Is this a limitation of the language? I can assign to a temporary variable to do the increment operation and then put the value back in the struct, but that seems clumsy.

推荐答案

代码使用modelsim 10.1d编译.我已经在 EDA Playground 上测试过了.

The code compiles with modelsim 10.1d. I have tested it on EDA Playground.

似乎 Aldec 工具不喜欢这条线:

Seems the Aldec tool does not like the line:

scorecard[tc_count].fail++;

作为一种解决方法，您可以用以下内容替换该行:

As a workaround you can replace the line with:

scorecard[tc_count].fail += 1;

现在它也可以使用 Aldec 工具进行编译.http://www.edaplayground.com/x/VpV

Now it compiles with Aldec tool as well. http://www.edaplayground.com/x/VpV

这篇关于SystemVerilog 结构体的单个变量可以用 ++ 递增吗?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！