如何建立,如果用一句话来比较不同的值? [英] How can I build if sentence with compare to various values?
问题描述
我怎么能写更好的方式本如果
语句条件?
IF((DATA_IN(8 DOWNTO 1)= X70)或(DATA_IN(8 DOWNTO 1)= X69)或
(DATA_IN(8 DOWNTO 1)= X72)或(DATA_IN(8 DOWNTO 1)= x的图7A)或
(DATA_IN(8 DOWNTO 1)= x的6B)或(DATA_IN(8 DOWNTO 1)= x的73),或
(DATA_IN(8 DOWNTO 1)= X74)或(DATA_IN(8 DOWNTO 1)= x的6C)或
(DATA_IN(8 DOWNTO 1)= x的75)或(DATA_IN(8 DOWNTO 1)= x的7D)),然后
data_make_ code< = DATA_IN(8 DOWNTO 1); - 回车键来缓冲
wrong_data&所述; ='0';
cnt_bit:= 0;
- 如果有效的键,然后
current_state< = break_ code_receive;
ELSIF
...
万一;
A 情况
语句可用于与多个值进行比较,而其他
的案例的一部分
可以被用来作为其他
,如:
情况下DATA_IN(8 DOWNTO 1)
当x70| x的69| X72| X7A| X6B|
X73| x的74| X6C| X75| X7D=>
... - 如果code的一部分
当别人=>
... - code的其他部分
结束的情况下;
另一种方法是使用 std_logic_vector
的阵列
的值,然后做一个功能,可以确定 DATA_IN
值等于任一值的数组中为止。在键入
和函数
声明可以那么无论是在架构
或过程
声明部分。然后VHDL-2008 code可以关注一下:
键入slv_array是阵列(自然分布和LT;>)std_logic_vector的;函数in_array(VAL:std_logic_vector;设置:slv_array)返回的布尔值是
开始
在set'range循环IDX
如果val =集(IDX),然后
返回TRUE;
万一;
结束循环;
返回FALSE;
结束功能;...如果in_array(DATA_IN,(X70,X69,X72,X7A,X6B
X73,X74,X6C,X75X7D)),然后
... - 如果code的一部分
其他
... - code的其他部分
万一;
另一种方法需要一些声明,但更普遍适用的。
How can i write this if
statement condition in better way?
if ((data_in(8 downto 1)=x"70") or (data_in(8 downto 1)=x"69") or
(data_in(8 downto 1)=x"72") or (data_in(8 downto 1)=x"7A") or
(data_in(8 downto 1)=x"6B") or (data_in(8 downto 1)=x"73") or
(data_in(8 downto 1)=x"74") or (data_in(8 downto 1)=x"6C") or
(data_in(8 downto 1)=x"75") or (data_in(8 downto 1)=x"7D")) then
data_make_code <= data_in (8 downto 1); -- enter key to buffer
wrong_data <='0';
cnt_bit :=0;
-- if valid key then
current_state <= break_code_receive;
elsif
...
end if;
A case
statement can be used to compare with multiple values, and the others
part of the case
can then be used as "else"
, like:
case data_in(8 downto 1) is
when x"70" | x"69" | x"72" | x"7A" | x"6B" |
x"73" | x"74" | x"6C" | x"75" | x"7D" =>
... -- if part of code
when others =>
... -- else part of code
end case;
An alternative method is to use an array
of std_logic_vector
with the values, and then make a function that can determine if the data_in
value equals either of the values in the array. The type
and function
declarations can then either be in the architecture
or process
declaration section. The code in VHDL-2008 can then look like:
type slv_array is array (natural range <>) of std_logic_vector;
function in_array(val : std_logic_vector; set : slv_array) return boolean is
begin
for idx in set'range loop
if val = set(idx) then
return TRUE;
end if;
end loop;
return FALSE;
end function;
...
if in_array(data_in, (x"70", x"69", x"72", x"7A", x"6B",
x"73", x"74", x"6C", x"75", x"7D")) then
... -- if part of code
else
... -- else part of code
end if;
The alternative method requires a few declarations, but is more general applicable.
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