如何使用依赖于实体的其他通用参数的通用参数? [英] How to use generic parameters that depend on other generic parameters for entities?

问题描述

我正在尝试转换一些 Verilog 代码，这些代码从 UART 模块的较快时钟产生较慢的时钟.原始 verilog 代码基于 fpga4fun.com 上的模块，这是我尝试将其转换为基于 VHDL 的设计.

I am trying to convert some Verilog code that produces a slower clock from a faster clock for a UART module. The original verilog code is based on the module over at fpga4fun.com, and this is my attempt to translate it for my VHDL-based design.

entity baud_generator is
generic(
    f_clk : integer := 50000000;  -- default: 50 MHz
    baud  : integer := 115200;    -- default: 115,200 baud
    accum_width : integer := 16;
    accum_inc : integer := (baud sll accum_width) / f_clk
);
port(
    clock : in std_logic;
    reset_n : in std_logic;
    enable : in std_logic;
    baud_clock : out std_logic
);  
end entity baud_generator;

但是，我的编译器 Aldec-HDL 不喜欢以下行:

However, my compiler, Aldec-HDL, doesn't like the following line:

 accum_inc : natural := (baud sll accum_width) / f_clk

这是确切的错误消息:

 # Error: COMP96_0300: baud_generator.vhd : (20, 52): Cannot reference "f_clk" until the interface list is complete.
 # Error: COMP96_0300: baud_generator.vhd : (20, 28): Cannot reference "baud" until the interface list is complete.
 # Error: COMP96_0071: baud_generator.vhd : (20, 28): Operator "sll" is not defined for such operands.
 # Error: COMP96_0104: baud_generator.vhd : (20, 27): Undefined type of expression.
 # Error: COMP96_0077: baud_generator.vhd : (20, 27): Assignment target incompatible with right side. Expected type 'INTEGER'.

在verilog中，我有这样的东西:

In verilog, I have something like this:

module baud_generator(
  input clock,
  input reset_n,
  input enable,
  output baud_clock
);
parameter f_clock = 50000000;
parameter baud    = 115200;
parameter accum_width = 16;
parameter accum_inc = (baud << accum_width) / f_clock;
//...
endmodule

我需要在该行中修改什么才能使编译器满意?是否可以使用像这样链接在一起的泛型?

What is it that I need to modify in that line to make the compiler happy? Is it possible to use generics chained together like that?

推荐答案

这基本上是说你不能用泛型值进行计算来计算(默认值)其他泛型.

This basically says you cannot do computations with the generic values to caluclate (default values for) other generics.

只需将 accum_inc 用作常量，而不是泛型.

Just use accum_inc as a constant, not as a generic.

此外，SLL(逻辑左移)运算符适用于ieee.numeric_std 中的位模式(unsigned 和 signed 数据类型和ieee.numeric_bit 包)，不适用于整数.您可以通过乘以 2 的幂来做同样的事情.

Also, the SLL (shift logic left) operator is meant for bit patterns (unsigned and signed datatypes in the ieee.numeric_std and ieee.numeric_bit packages), not for integers. You can do the same by multiplying by a power of two.

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