VIM 高亮匹配开始/结束 [英] VIM highlight matching begin/end
问题描述
我正在尝试找到一个插件,该插件将使用 Verilog 突出显示匹配的开始/结束语句.VIM 让它与花括号/括号一起工作,但它不能与它的开始/结束一起工作.我希望 VIM 突出显示正确的开始到正确的结束.
I'm trying to find a plugin that will highlight the matching begin/end statements with Verilog. VIM has it working with curly braces /brackets but it does not work with its begin/end. I want VIM to highlight the correct begin to the correct end.
推荐答案
在我看来,最好的办法是使用 matchit.此脚本是 vim 运行时的一部分,可以通过将以下行添加到 .vimrc 中轻松加载:
In my opinion, your best bet is using matchit. This script is part of vim runtime and can easily be loaded by adding the following line to your .vimrc:
runtime macros/matchit.vim
标准的 Verilog 文件类型插件已经包含您需要的 matchit 配置:
The standard Verilog filetype plugin already includes the matchit configuration you require:
" Let the matchit plugin know what items can be matched.
if exists("loaded_matchit")
let b:match_ignorecase=0
let b:match_words=
\ '\<begin\>:\<end\>,' .
\ '\<case\>\|\<casex\>\|\<casez\>:\<endcase\>,' .
\ '\<module\>:\<endmodule\>,' .
\ '\<if\>:\<else\>,' .
\ '\<function\>:\<endfunction\>,' .
\ '`ifdef\>:`else\>:`endif\>,' .
\ '\<task\>:\<endtask\>,' .
\ '\<specify\>:\<endspecify\>'
endif
通过这种方式,您可以使用 %
键匹配开始/结束,就像您可能已经为括号等所做的那样.
This way you can match the begin/end using %
key, as you probably already do for parentheses and such.
这并不完全是您要查找的内容,因为尽管它允许您找到开头的匹配结尾,但它并没有为您突出显示它.我做了一些研究,显然有一个代码片段;并且有人已经将该代码转换为插件,名为 hl_matchit.不要忘记查看此插件的帮助页面:
This is not exactly what you were looking for, in the sense that although it allows you to find the matching end of a begin it does not highlight it for you. I did some research and apparently there's a code snippet around for that; and there's someone who already transformed that code into a plugin, which is named hl_matchit. Don't forget to check this plugin's help page:
:help hl_matchit.txt
请注意,vim 安装中包含的 Verilog 文件类型插件不支持 Verilog 2001 中引入的 ifndef
和 elsif
子句.如果您需要这个,我建议您还安装前面已经提到的 verilog_systemverilog.vim 插件,但使用 fork 我正在改进,其中包括前面提到的更新,以及其他修复/改进.
Please note that the Verilog filetype plugin included in vim installation does not support the ifndef
and elsif
clauses introduced in Verilog 2001. If you require this then I suggest that you also install the verilog_systemverilog.vim plugin already mentioned before, but use the fork I am improving which includes the afore mentioned updates, as well as other fixes/improvements.
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