SystemVerilog 数据类型的差异(reg、logic、bit) [英] Difference of SystemVerilog data types (reg, logic, bit)

问题描述

systemverilog 中有不同的数据类型可以使用，如下所示:

There are different data types in systemverilog that can be used like the following:

reg [31:0] data;
logic [31:0] data;
bit [31:0] data;

他们三个有何不同?

推荐答案

reg 和 wire 是原始类型.不断分配连线并在特定点评估 regs，这里的优势是模拟器可以进行优化.

reg and wire were the original types. Wires are constantly assigned and regs are evaluated at particular points, the advantage here is for the simulator to make optimisations.

wire w_data;
assign w_data = y;

// Same function as above using reg
reg r_data;
always @* 
  r_data = y ;

学习 Verilog 时的一个常见错误是假设 a reg 类型意味着硬件中的寄存器.模拟器的早期优化可以通过它的使用上下文来完成.

A common mistake when learning Verilog is to assume the a reg type implies a register in hardware. The earlier optimisation for the simulator can be done through the context of its usage.

这引入了logic，它可以用来代替wire和reg.

This introduces logic which can be used in place of wire and reg.

logic  w_data;
assign w_data = y;

// Same function as above using reg
logic r_data;
always @* 
  r_data = y ;

类型 bit 和 byte 也被创建，它们只能保存 2 个状态 0 或 1 没有 x 或 z.byte 意味着 bit [7:0].使用这些类型可以稍微提高速度，但我建议不要在 RTL 中使用它们，因为您的验证可能会错过未初始化的值或关键重置.

The type bit and byte have also been created that can only hold 2 states 0 or 1 no x or z. byte implies bit [7:0]. Using these types offers a small speed improvement but I would recommend not using them in RTL as your verification may miss uninitialized values or critical resets.

bit 和 byte 的使用在测试平台组件中更常见，但在必须驱动 x 以刺激数据损坏和恢复的情况下可能会导致问题.

The usage of bit and byte would be more common in testbench components, but can lead to issues in case of having to drive x's to stimulate data corruption and recovery.

更新

在撰写本文时，我的印象是 logic 不能用于三态，我无法找到以此为基础的原始论文.在进一步更新、评论或编辑之前，我撤销我关于逻辑不能用于创建三态线的断言.

At the time of writing I was under the impression that logic could not be used for tristate, I am unable to find the original paper that I based this on. Until further updates, comments or edits, I revoke my assertion that logic can not be used to create tri-state lines.

添加了 tri 类型，用于明确定义三态线.它基于wire的属性，logic基于reg的属性.

The tri type has been added, for explicitly defining a tri-state line. It is based on the properties of a wire, logic is based on the properties of a reg.

tri t_data;
assign t_data = (drive) ? y : 1'bz ;

如果您不再需要支持向后兼容 Verilog，那么我建议您改用 logic 和 tri.使用 logic 有助于重构，并且 tri 反映了三态线的设计意图.

If you no longer have to support backwards compatibility Verilog then I would recommend switching to using logic and tri. Using logic aids re-factoring and and tri reflects the design intent of a tristate line.

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