如何在 Verilog 中定义和初始化仅包含向量的向量? [英] How to define and initialize a vector containing only ones in Verilog?

问题描述

如果我想声明一个包含所有 1 的 128 位向量，这些方法中哪一种总是正确的?

If I want to declare a 128 bit vector of all ones, which one of these methods is always correct?

wire [127:0] mywire;

assign mywire = 128'b1;
assign mywire = {128{1'b1}};
assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

推荐答案

正如快速模拟所证明的那样，assign mywire = 128'b1; 不会分配 mywire 的所有位code> 到 1.只有位 0 被赋值为 1.

As a quick simulation would prove, assign mywire = 128'b1; does not assign all bits of mywire to 1. Only bit 0 is assigned 1.

以下两种情况总是将所有 128 位都分配为 1:

Both of the following always assign all 128 bits to 1:

assign mywire = {128{1'b1}};
assign mywire = 128'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF;

第一行的一个优点是它更容易扩展到大于和小于 128 的宽度.

One advantage of the 1st line is that it is more easily scalable to widths greater than and less than 128.

对于 SystemVerilog，以下语法也总是将所有 128 位都赋值为 1:

With SystemVerilog, the following syntax also always assigns all 128 bits to 1:

assign mywire = '1;

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