如果敏感性列表中的变量缺失，将创建什么逻辑 [英] What logic will be created if variables in the sensitivity list are missing

问题描述

这是美国排名前 10 的公司提出的面试问题.

This was an interview question asked by a top 10 company of US.

代码 1:

always @(a or b or sel) begin 
  if (sel == 1)
  c = a; 
  else if (sel == 0) 
  c =b; 
end 

这将创建一个多路复用器.

This will create a mux.

代码 2:现在SEL"从敏感性中删除.它还会创建多路复用器吗?对于下面的代码?如果不是，将创建什么逻辑?

Code 2: Now "SEL" is removed from sensitivity. Will it still create mux? For the code below? If not, what logic will be created?

always @(a or b) begin 
  if (sel == 1)
  c = a; 
  else if (sel == 0) 
  c =b; 
end 

推荐答案

是的，这仍会合成到多路复用器¹.综合工具将解释此 RTL，就好像敏感度列表是完整的一样.

Yes, this will still synthesize to a multiplexer¹. A synthesis tool will interpret this RTL as if the sensitivity list were complete.

然而，这里出现了一个大问题，因为与门级模拟/实际芯片相比，您会在 RTL 模拟中看到不同的行为.在您的 RTL 模拟中，如果 a 或 b 发生变化，c 只会变化.如果只有多路复用器的选择信号 sel 发生变化，您的输出 c 在 RTL 模拟中不会发生变化.

However, a large issue here arises because you will see different behaviour in your RTL simulations compared to the gate-level simulations/the actual silicon. In your RTL simulation, c will only change if a or b change. If only the select-signal sel of the multiplexer changes, your output c will not change in RTL simulations.

当打算创建组合逻辑时，通常建议使用

When intending to create combinatorial logic, it is generally advisable to use

always @(*)

或

always_comb

如果您可以使用 SystemVerilog.这样做的好处是您永远不会遇到与敏感性列表相关的模拟/综合不匹配.后一个关键字还有一个优点，即您可以明确告诉工具您想要创建组合逻辑(而不是非预期的锁存器，例如).

if you can use SystemVerilog. This has the advantage that you never run into sensitivity-list related simulation/synthesis mismatches. The latter keyword furthermore has the advantage that you explicitly tell tools that you want to create combinatorial logic (rather than unintended latches, for example).

最后:Mills &Cummings 写了一篇关于RTL 编码样式导致模拟和综合不匹配的精彩论文.在许多其他问题中，这个问题在这里得到了很好的描述.我非常推荐看一下这篇论文！

Finally: Mills & Cummings wrote a great paper on RTL Coding Styles That Yield Simulation and Synthesis Mismatches. This issue, among many others, is described here very well. I can greatly recommend to take a look at this paper!

正如您在评论中指出的，您想知道 sel === 1'bx 会发生什么.为了更好地理解这个问题，我强烈建议阅读 我'm 仍然爱着我的 X！ 作者:斯图尔特·萨瑟兰.我将在此处对您的特定示例进行非常简短的总结.

As you indicated in your comment, you were wondering what would happen is sel === 1'bx. To better understand this matter, I highly recommend reading I'm Still In Love With My X! by Stuart Sutherland. I will give a very brief summary on your particular example here.

SystemVerilog 中的条件块倾向于 X 乐观，在上述论文中定义为:

Conditional blocks in SystemVerilog are prone to X-optimism, which is defined in the aforementioned paper as:

X 乐观已被定义为 [...] 任何时候模拟将输入到操作或逻辑门的 X 值转换为输出上的 0 或 1.[...] SystemVerilog 可能过于乐观，这意味着当实际硅片仍然不明确时，X 在模拟中传播为 0 或 1.

X-optimism has been defined [...] as any time simulation converts an X value on the input to an operation or logic gate into a 0 or 1 on the output. [...] SystemVerilog can be overly optimistic, meaning an X propagates as a 0 or 1 in simulation when actual silicon is still ambiguous.

在查看您的代码时，我们会看到 sel === 1'bx 将不会传播到 c.相反，模拟器将保存 c 的先前值并模拟锁存器.这过于 X 乐观，并且是与实际硅片的模拟不匹配，因为这里的选择线将不是 X:信号是 1 或 0.换句话说，这将不是是一个锁存器在硅！

When looking at your code, we will see that an sel === 1'bx will not propagate to c. Rather, the simulator will hold the previous value of c and mimic a latch. This is overly X-optimistic and is a simulation mismatch with actual silicon, since the select line will not be X here: a signal is either 1 or 0. In other words, this will not be a latch in silicon!

一种解决方案可能是在模拟中使多路复用器 X 悲观，以便我们可以检测到这种不确定状态.为此，当 sel 既不是 0 也不是 1 时，我们将 X 分配给 c:

One solution could be to make the multiplexer X-pessimistic in simulation, so that we would detect this undetermined state. To do so, we assign X to c when sel is neither 0, nor 1:

always_comb
    if (sel)
        c = a; 
    else if (!sel) 
        c = b; 
`ifndef SYNTHESIS // see footnote 2
    else
        c = 'x;
`endif

然而，这有一个问题，那就是它过于悲观了.当 a 和 b 具有相同的值时，我们将清楚地知道 c 在实际芯片中的值(无论 c代码>sel).

This has the problem, however, that it is overly pessimistic. When both a and b have the same value, we would unambiguously know what value c would have in actual silicon (regardless of the value of sel).

上述论文给出了条件运算符 (? :) 作为可能的解决方案:

The aformentioned paper gives the conditional operator (? :) as a possible solution:

条件?表达式 1 : 表达式 2;

如果条件计算结果为未知，则运算符对表达式 1 和表达式 2 的值进行逐位比较.对于每个位位置，如果该位在两个表达式中均为 0，则为该位返回 0.如果两个位都为 1，则返回 1.如果每个表达式中对应的位不同，或者Z，或者X，则为那个位返回一个X

If the condition evaluates to unknown, the operator does a bit-by-bit comparison of the values of expression1 and expression2. For each bit position, if that bit is 0 in both expressions, then a 0 is returned for that bit. If both bits are 1, a 1 is returned. If the corresponding bits in each expression are different, or Z, or X, then an X is returned for that bit

因此，通过使用下面的代码，我们可以在上述两种解决方案之间进行折衷:

So, by using the code below, we would have a compromise between the two aforementioned solutions:

always_comb
    c = sel ? a : b;

这里的缺点是条件运算符不适合更复杂的表达式.

The downside here is that the conditional operator is not suited for more complex expressions.

总结的三种方法:

╭───────────╥─────────────────────────────────────────────────╮      
│   input   ║                     sel(t)                      │
├───╥───╥───╫────────────┬─────────────┬────────────┬─────────┤
│sel║ a ║ b ║ optimistic │ pessimistic │ compromise │ silicon │
╞═══╬═══╬═══╬════════════╪═════════════╡════════════╪═════════╡
│ X ║ 0 ║ 0 ║  sel(t-1)  │      X      │     0      │    0    │
│ X ║ 0 ║ 1 ║  sel(t-1)  │      X      │     X      │   0/1   │
│ X ║ 1 ║ 0 ║  sel(t-1)  │      X      │     X      │   0/1   │
│ X ║ 1 ║ 1 ║  sel(t-1)  │      X      │     1      │    1    │
└───╨───╨───╨────────────┴─────────────┘────────────┴─────────┘

在他的论文中，Sutherland 给出了另一个我同意的解决方案:最好使用断言来检测导致 X 的设计问题，而不是让 X 在设计中传播并花费大量时间寻找根本原因.对于您的特定代码，这可能如下所示:

In his paper, Sutherland gives another solution with which I agree: It is best to use assertions to detect design issues which cause X, instead of letting X propagate through the design and spending a lot of time finding the root cause. For your particular code, this could look like this:

always_comb
begin
    assert (!$isknown(sel))
    else $error("sel = X!");

    if (sel)
        c = a; 
    else if (!sel) 
        c = b; 
 end

---

^{1:我在这里假设 sel 是一个 1 位信号.否则，你最终会得到一个闩锁}

---

^{1: I assume here that sel is a 1-bit signal. Otherwise, you would end up with a latch}

^{2:在这里查看我的答案 有关 SYNTHESIS 宏标识符的更多信息.}

^{2: See my answer here for some more information on the SYNTHESIS macro identifier.}

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