systemverilog ->从实例化另一个接口的接口传递参数 [英] systemverilog -> Passing parameters from an interface that instantiates another interface

问题描述

我正在尝试将接口传递给作为接口数组的模块.

I'm trying to pass an interface to a module which is an array of interfaces.

interface front_port #(parameter DATA_WIDTH = 4);
        logic   [DATA_WIDTH - 1 : 0]   data;
        logic                          acknowledge;

        modport f_interface(input data, output acknowledge);
endinterface

interface front_interface #(parameter NO_OF_IN_PORTS = 3);
        front_port    front_ports[NO_OF_IN_PORTS]();
endinterface

module A #(parameter NO_OF_IN_PORTS = 3)
(
    interface front_port;
);

module testbench;
    font_interface #(.NO_OF_IN_PORTS(3))  my_front_interface();

    A #(.NO_OF_IN_PORTS(3)) (.front_port(my_front_interface));
endmodule

那么，我的问题是，my_front_interface 的数组元素是否可以具有不同的 DATA_WIDTH 值.如果是这样，如何?在上面定义的代码中，my_front_interface 的所有数组元素的默认DATA_WIDTH 为 4.

So, my question is, can the array elements of my_front_interface have different values of DATA_WIDTH. If so, how? In the code defined above all the array elements of my_front_interface have the default DATA_WIDTH of 4.

谢谢

推荐答案

根据我的评论，在给定的代码中似乎有很多编译错误.但是，我已经尝试按照我的理解来解决它们.

Following from my comments, there seems many compilation errors in the given code. Yet, I have tried to resolve them as per my understanding.

为了创建变化的 DATA_WIDTH 实例，接口front_interface 必须在各种实例中获取有关DATA_WIDTH 的信息.因此，向front_interface 实体添加一组参数.该数组的大小由NO_OF_IN_PORTS参数决定.

In order to create varying DATA_WIDTH instances, the interface front_interface must get information about DATA_WIDTH in various instances. So, adding an array of parameters to front_interface entity. The size of that array is determined by NO_OF_IN_PORTS parameter.

此外，您必须使用 generate 块来创建 front_port 的多个实例.每个实例从front_interface 实体的参数数组 中选取一个元素.

Further, you must use generate block for creating multiple instances of front_port. Each instance picks up an element from parameter array of front_interface entity.

我创建了以下代码，它覆盖DATA_WIDTH的默认值，并创建具有唯一数据宽度的实例.

I have created following code which overrides the default values of DATA_WIDTH and creates instances with unique data widths.

interface front_port #(parameter DATA_WIDTH = 4);
    logic   [DATA_WIDTH - 1 : 0]   data;
    logic                          acknowledge;

    modport f_interface(input data, output acknowledge);

  initial
    begin : DEBUG_DISPLAY
      $display("DATA_WIDTH for %m is %0d",DATA_WIDTH);
    end
endinterface

// Use array DATA_WIDTH here, for varying data widths.
interface front_interface #(parameter NO_OF_IN_PORTS = 3, int DATA_WIDTH[NO_OF_IN_PORTS] = '{1,2,3});
  genvar i;
  generate // generate block for multiple instances
    begin : MULTIPLE_INSTANCES
      for(i=0;i<NO_OF_IN_PORTS;i++)
        begin : UNIQUE_DATA_WIDTH
          // Pick up each element from array to create varying DATA_WIDTH instances
          front_port #(.DATA_WIDTH(DATA_WIDTH[i])) front_ports();
        end
     end
  endgenerate
endinterface

module A #(parameter NO_OF_IN_PORTS = 3)
          (front_interface fi_if);
endmodule

module testbench;

  // Override DATA_WIDTH here for different instances
  front_interface #(.NO_OF_IN_PORTS(3), .DATA_WIDTH('{4,5,6}))  my_front_interface();

  A #(.NO_OF_IN_PORTS(3)) a1(my_front_interface);

endmodule

输出:

DATA_WIDTH for testbench.my_front_interface.MULTIPLE_INSTANCES.UNIQUE_DATA_WIDTH[0].front_ports.DEBUG_DISPLAY is 4
DATA_WIDTH for testbench.my_front_interface.MULTIPLE_INSTANCES.UNIQUE_DATA_WIDTH[1].front_ports.DEBUG_DISPLAY is 5
DATA_WIDTH for testbench.my_front_interface.MULTIPLE_INSTANCES.UNIQUE_DATA_WIDTH[2].front_ports.DEBUG_DISPLAY is 6

请参阅此页面以传递数组实体中的参数.此外，SystemVerilog IEEE 1800-2012 第 27 节对 <代码>生成块.

Refer this page for passing array of parameters in an entity. Also, SystemVerilog IEEE 1800-2012 Section 27 is helpful for generate blocks.

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