驱动模块输入 [英] Driving module input

问题描述

我在一些 EDA 游乐场进行了一些测试，以检查当模块中的某些输入被驱动时，模拟器工具报告了什么.

I made some tests in some EDA playground, to check what simulator tools are reporting when in a module some inputs are driven.

这里是 eda 游乐场链接:https://www.edaplayground.com/x/5qK4

Here is eda playground link : https://www.edaplayground.com/x/5qK4

因此，根据我的实验，该工具在执行此类操作时报告某些错误的唯一方法是在定义输入时使用 var 关键字.

So from my experiment the only way the tool is reporting some error when doing such thing is using the var keyword when defining the input.

有人可以解释为什么三种不同的输入声明方式之间存在差异吗?

Can someone explain why there is difference between the three different way to declare the input ?

我想这意味着您可以在将其声明为线路时进行端口强制

I guess that means you can do port coercion when declaring it as wire

我也把代码贴在这里

module test(
  input var logic a,
  input logic b,
  input c
);

assign a = 1'b0;
assign b = 1'b0;
assign c = 1'b0;

endmodule

推荐答案

这是一个逻辑类型的输入变量:

This is an input variable of type logic:

 input var logic a,

对此没有任何争议，因为每个都已明确声明*.

There's no debate about that because each is explicitly declared*.

IEEE 1800-2012 的第 23.2.2.3 节说(端口种类是 var 或 wire):

Section 23.2.2.3 of IEEE 1800-2012 says (the port kind is var or wire):

如果省略端口种类: — 对于输入和输入端口，端口应默认为默认网络类型的网络.默认的网络类型可以使用 `default_nettype 编译器指令

If the port kind is omitted: — For input and inout ports, the port shall default to a net of default net type. The default net type can be changed using the `default_nettype compiler directive

因此，因为默认的default_nettype是wire，所以这是一个logic类型的输入wire:

Therefore, because the default default_nettype is wire, this is an input wire of type logic:

input logic b,

IEEE 1800-2012 的第 23.2.2.3 节还说:

Section 23.2.2.3 of IEEE 1800-2012 also says:

如果省略数据类型，则默认为逻辑，除了没有数据类型的互连端口

If the data type is omitted, it shall default to logic except for interconnect ports which have no data type

因此这是logic类型的输入wire:

input c

如果变量已经从其他地方驱动，那么从赋值语句驱动变量肯定是非法的，所以这行绝对不好:

Now it is certainly illegal to drive a variable from an assign statement if it is already driven from somewhere else, so this line is definitely no good:

assign a = 1'b0;

因为输入 a 绝对是一个变量 - 这是显式的.但是如果我们把它改成(比如说)

Because input a is definitely a variable - that is explicit. But if we change that to (say)

always_comb a = 1'b0;

那么还是不行，因为输入被认为是使用 assign 语句驱动变量 a 并且，正如我们已经知道的，驱动是非法的来自赋值语句的变量，如果它已经从其他地方驱动了.

then it's still no good, because the input is considered to be driving the variable a using an assign statement and, as we already know, it is illegal to drive a variable from an assign statement if it is already driven from somewhere else.

然而，因为 b 和 c 是网络(wire)，所以可以从多个地方驱动它们，所以这些行应该没问题:

However, because b and c are nets (of kind wire), it is fine to drive them from more than one place, so these lines should be OK:

assign b = 1'b0;
assign c = 1'b0;

<小时>

*没有项目因为打字太长而迟到.因此，为什么不这样做呢?

---

*No project was ever late because the typing too too long. Therefore, why not just do this?

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