verilog中的花括号 [英] Curly braces in verilog

问题描述

我浏览了一个程序，发现了以下代码:

I was looking through a program and found the following code:

{a2, a1} <= {a1, b};

我不确定我正在经历的程序是用 Verilog 还是 SystemVerilog 编写的.我知道花括号用于 Verilog 中的连接操作，但是我不太了解这里正在完成什么样的连接.此外，由于我不确定给定的代码片段是使用 Verilog 还是 SystemVerilog，因此我对代码感到困惑.花括号是否还表示 SystemVerilog 中的另一个操作…?

I am not sure whether the program that I'm going through is written in Verilog or SystemVerilog. I know the curly braces are used for concatenation operation in Verilog, but then I don't quite follow what kind of concatenation is being done here. Also since I'm not sure whether the given snippet is in Verilog or SystemVerilog, I'm left confused with the code. Also does curly braces denote another operation in SystemVerilog…?

提前致谢

推荐答案

这只是将左右两侧各视为一个变量的串联.SystemVerilog 2009 取代了 Verilog，因此向后兼容大多数(所有?)语法.

This is just concatenation treating the Left and right hand side as one variable each. SystemVerilog 2009 replace Verilog, so is backwards compatible with most (all?) syntax.

例如

wire [0:0] l1;
wire [2:0] l2;
reg  [1:0] r1;
reg  [1:0] r2;

assign {l1,l2} = {r1,r2} ;

与

assign l1[0] = r1[1];
assign l2[2] = r1[0];
assign l2[1] = r2[1];
assign l2[0] = r2[0];

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