系统 Verilog always_latch 与 always_ff [英] System Verilog always_latch vs. always_ff

问题描述

刚开始学习 System Verilog.我对语句 always_ff 和 always_latch 的使用感到困惑.前者将用作:

always_ff @ (posedge clk)开始a <= b;结尾

而后者:

always_latch开始a <= b;结尾

第一个仅由时钟的上升沿激活，并与非阻塞分配相结合产生 FF.

always_latch 显然被认为代表了一个锁存器，但是为什么要使用非阻塞赋值呢?使用带有阻塞赋值的 always_comb 不是更好吗?

解决方案

通过使用 always_latch 或 always_ff，设计人员意图分别推断锁存器或时序逻辑，但如果逻辑不正确，软件工具可以警告设计人员未正确推断预期的硬件逻辑.

例如:

always_ff @(posedge clk 或 negedge rst)开始如果(！第一个)一个 <= '0;结尾

对于上面的代码，设计者打算只得到一个时序逻辑而不是一个锁存器，但实际上会生成一个锁存器(任何静态工具都会生成一个警告消息，如Latch will be inferred for the logic")

>

与下面的代码类似，设计人员的意图是推断硬件锁存器，以便工具(更好地理解您的逻辑)并且不会报告它.

 always_latch开始如果(第一个)a <= b;结尾

锁存器是一种时序逻辑，作用于时钟电平而不是时钟边沿.

一般来说，最佳实践是对顺序逻辑使用非阻塞赋值，对组合逻辑使用阻塞赋值，这在第 5.0 节中有详细说明Verilog Synthesis 中的非阻塞赋值，致命的编码风格><块引用>

指南#2:建模锁存器时，使用非阻塞赋值.

Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch. The former would be used as:

always_ff @ (posedge clk)
begin
    a <= b;
end

while the latter:

always_latch
begin
    a <= b;
end

The first is activated just by the positive edge of the clock and coupled with non-blocking assignment produces a FF.

The always_latch is obviously thought to represent a latch, but then why use a non-blocking assignment? Wouldn't be better using a always_comb with blocking assignments?

解决方案

By using always_latch or always_ff a designers intent to infer a latch or a sequential logic respectively, but if the logic is not correct software tools can warn the designer that the intended hardware logic is not inferred properly.

eg:

always_ff @ (posedge clk or negedge rst) 
begin
  if (!rst)
    a <= '0;
end

For the above code the designer intended to get only a sequential logic and not a latch but a latch would be generated in actual (Any static tool will generate a warning message as "Latch will be inferred for the logic")

Similarly for the below code the designers intent is to infer a hardware latch so tool will(understand your logic better) and won't report it.

    always_latch
    begin
      if (rst)
        a <= b;
    end

Latch is a sequential logic which works on levels of clocks instead of clock edges.

In general best practice is to use Non-blocking assignments for sequential logic and blocking assignments for combinatorial logic which is explained in detail under Section 5.0 Verilog coding guidelines of Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

Guideline #2: When modeling latches, use nonblocking assignments.

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