输入信号与阵列值进行比较 [英] Comparing input signal with array values
问题描述
我在previous后综合的数组值
我想用Verilog创建一个数组来存储 X
,一个给定的功能是
值。
现在我想比较此阵的X
值的输入。如果该值是一个特定的区域内我要救这个地区的指数,执行与是
具有相同索引的加法。结果进到输出。在code编译得很好,但它不是综合的电路。这个想法后来就是用这个数组进行线性插值和定是
的值的给定值 X
它不是数组中。的code是如下。我保存 X
和是
每个索引的保存价值。
模块MEMC(INP,OUTP,CLK,复位);
输入[2:0] INP;
输入时钟,复位;
输出[2:0] OUTP;
REG [2:0] OUTP;
线[2:0]测试;
章第[5:0] MEM [2:0];总是@(posedge时钟)
如果(复位== 1'b1的)开始
MEM [0]&下; = {3'b000,3'b000}; // Y0,X0
MEM [1] = {3'b001,3'b001}; // Y1,X1
MEM [2]所述; = {3'b010,3'b010}; // Y2,X2
结束
分配试验= {INP&下; MEM [0] [2:0],磷化铟及所述; MEM [1] [2:0],磷化铟及所述; MEM [2] [2:0]}; //用XO,X1,X2 INP比较创建测试矢量
总是@(测试)
情况下(试验)
3'b1xx:OUTP = MEM [0] [2:0] + MEM [0] [5:3]; //如果0℃; INP&下; X1
3'b0xx:OUTP = MEM [1] [2:0] + MEM [1] [5:3]; //如果X1&所述; INP&下; X2
3'b00x:OUTP = MEM [2] [2:0] + MEM [2] [5:3]; //如果X2&所述; INP&下; X3的
默认:OUTP = 3'b00;
ENDCASE
endmodule
首先,所有三个你的如果
条件是相同的( INP&GT ; MEM [0] [2:0]
)。我假设你想
总是@(*)
开始
如果(INP> MEM [0] [2:0])//索引0
开始
索引= 0;
结束
否则如果(INP> MEM [1] [2:0])//指数1
开始
索引= 1;
结束
否则如果(INP> MEM [2] [2:0])//指数2
开始
索引= 2;
结束
结束
其次,如果你使用的是大阵(硬确切的大小),从INP潜伏期 - > OUTP会很长,你可能会得到时序违规,根据您的时钟速度。在这种情况下,你会过建立一个非常简单的FSM,并检查每时钟周期一个或两个项目,而不是更好。只是要记住前进。
As I wrote in my previous post Synthesizable array of XY values
I wanted to create an array in Verilog to store x
, y
values of a given function.
Now I want to compare an input with x
values of this array. If the value is within a specific region I want to save the index of this region and perform an addition with y
with the same index. The result goes to the output. The code compiles just fine but its not synthesizes any circuit. The idea later is to use this array to perform linear interpolation and determinate the value of y
for a given value of x
that its not inside the array. The code is the following. I save the save value for x
and y
for each index.
module memc (inp,outp,clk,reset);
input[2:0] inp;
input clk, reset;
output[2:0] outp;
reg[2:0] outp;
wire [2:0] test;
reg [5:0] mem[2:0];
always @(posedge clk)
if (reset == 1'b1) begin
mem[0] <= {3'b000, 3'b000};//y0,x0
mem[1] <= {3'b001, 3'b001};//y1,x1
mem[2] <= {3'b010, 3'b010};//y2,x2
end
assign test ={inp<mem[0][2:0],inp<mem[1][2:0],inp<mem[2][2:0]}; //create a test vector by comparing inp with xo,x1,x2
always @(test)
case (test)
3'b1xx: outp=mem[0][2:0]+mem[0][5:3];//if 0<inp<x1
3'b0xx: outp=mem[1][2:0]+mem[1][5:3];//if x1<inp<x2
3'b00x: outp=mem[2][2:0]+mem[2][5:3];//if x2<inp<x3
default: outp=3'b00;
endcase
endmodule
Firstly, all three of your if
conditions are the same (inp > mem[0][2:0]
). I'm assuming you want
always @(*)
begin
if (inp > mem[0][2:0] ) //index 0
begin
index = 0;
end
else if (inp > mem[1][2:0] ) // index 1
begin
index = 1;
end
else if(inp > mem[2][2:0] ) // index 2
begin
index = 2;
end
end
Secondly, if you are using a large array (hard to be exact on the size), the latency from inp -> outp will get quite long, and you may get timing violations, depending on your clock speed. In that case, you'd be better off building a very simple FSM, and checking one or two entries per clock cycle instead. Just something to keep in mind moving forward.
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