为什么信号不会在过程语句中立即更新?VHDL [英] Why won't a signal be updated instantly in process statement? VHDL

问题描述

在 VHDL 中，您需要在 process 语句中使用一个变量，以便它立即更新.可以使用信号，但不会立即更新.重复我上面的问题:为什么不能在进程语句中立即更新信号?

In VHDL, you need to use a variable in a process statement for it to be updated instantaneously. The use of a signal can be done, but it won't be updated immediately. Repeating my question from above: Why won't a signal be updated instantly in process statement?

推荐答案

因为 signal 被设计为在硬件中表现得像一个物理实现的值，它只更新响应确定的刺激并根据随着时间的推移.

Because a signal is designed to behave like a physically implemented value in the hardware, it only updates in response to determined stimuli and according to the progression of time.

在 VHDL 中，这反映在信号赋值语句本身不会更新 signal 的值.相反，它会安排在该信号上发生的事务，当指定的时间到来时，将触发该信号上的事件以更改其值(如果分配是更改的值).

In VHDL, this is reflected in that a signal assignment statement does not itself update the value of a signal. Rather, it schedules a transaction to occur on that signal that, when the appointed time comes, will trigger an event on the signal to change its value (if the assignment is to a changed value).

事务的默认调度是在模拟中的增量延迟之后，即模拟时刻就在所有并发执行的进程完成之后.因此，如果我在时钟进程中操作并更新由 rising_edge(clk) 触发的进程中的信号值，则在该进程的当前运行中将无法访问新值，但会更新就在时钟的上升沿之后，当过程完成时.

The default scheduling for a transaction is after a delta-delay in simulation, i.e. a simulation time instant just after all concurrently executing processes at that time complete. So if I'm operating in a clocked process and I update a signal value in a process triggered by rising_edge(clk), the new value won't be accessible within that current run of the process but will update just after the rising edge of the clock, when the process is complete.

之所以存在这种差异，是因为 VHDL 是一种硬件描述语言，而不是一种编程语言.因此，设计必须考虑硬件操作的实际情况——时间的进展、对因果刺激的需要等等.因此，在一个好的 VHDL 设计中，任何意味着在时间中持续存在的值都将被定义为一个信号，以便设计考虑到它应该像硬件的一部分一样工作.在一个过程中，变量可以提供一个用于组合计算的中间值——合成器将确定完成该工作所需的任何逻辑，但变量作为一个语言元素是一种计算工具，而不是定义持久值的方法.当然，variable 滥用是可能的，而且确实存在...... :^)

This difference exists because VHDL is a hardware description language, not a programming language. Designs therefore must take into account the realities of hardware operation - the progression of time, the need for causal stimuli, &c. Thus in a good VHDL design, any value meant to persist through time will be defined as a signal so that the design takes into account that it ought to behave like a section of hardware. Within a process, a variable can provide an intermediate value for use in a combinatorial calculation - the synthesizer will determine whatever logic is necessary to accomplish that job, but the variable as a language element is a tool for calculations, not a way to define persistent values. Of course, variable abuse is possible and does exist... :^)

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