什么是推断的闩锁以及在 if 条件中缺少 else 语句时如何创建它.有人能简单解释一下吗? [英] What is inferred latch and how it is created when it is missing else statement in if condition. Can anybody explain briefly?

问题描述

我试图找出推断的闩锁以及为什么内部需要它，但我找不到任何足够详细的资源.

I tried to figure out the inferred latch and why it is needed internally, but I couldn't find any resources with enough detail.

推荐答案

在未将网络分配给已知值的组合块中推断出锁存器.为自己分配一个网络仍然会推断出一个锁存器.锁存器也可以通过丢失的信号来推断，形成一个灵敏度列表和反馈回路.

A latch is inferred within a combinatorial block where the net is not assigned to a known value. Assign a net to itself will still infer a latch. Latches can also be inferred by missing signals form a sensitivity list and feedback loops.

在 Verilog/SystemVerilog 中推断预期锁存器的正确方法是:

The proper way of inferring a intended latch in Verilog/SystemVerilog are:

/* Verilog */       ////    /* SystemVerilog */
always @*           ////    always_latch
begin               ////    begin
  if (en) q = d;    ////      if (en) q = d;
end                 ////    end

意外推断闩锁的方式:

• 敏感度列表缺少信号(这就是应该使用 @* 的原因):

  always @(a or b) // inferred latch :: "c" missing for the sensitivity list.
  begin
    out = a + b + c;
  end
  

• 缺少条件:

• Missing Condition:

  always @*
  begin
    case(in[1:0])
     2'b00:  out = 1'b0;
     2'b01:  out = 1'b1;
     2'b10:  out = 1'b1;
     // inferred latch "out" :: missing condition 2'b11/default
   endcase
  end
  always @*
  begin
    next0 = flop0;
    next1 = flop1;
    // inferred latch "next2" :: missing initial condition
    next3 = flop3;
    case(a[2:0])
     3'b001:             next0 = in;
     3'b010:  if(b)      next1 = in;
     3'b100:  if(c)      next2 = in;
     default: if(!b&&!c) next3 = in;
   endcase   
  end
  

• 反馈循环:

• Feedback Loop:

  assign out = en ? in : out; // inferred latch "out" :: feedback to mux
  assign a = en ? z : c;
  // ... any amount of code between ...
  assign z = en ? a : y; // inferred latch "a" :: feedback chain
  

  • 反馈循环可以遍历层次结构和设计.
  • 使预期的闩锁简单易识别:
    • 使用尽可能少的组合逻辑将预期的锁存器放在它们自己的 always 块中；理想情况下，将锁存器的组合逻辑放在其自己单独的 always 块中.尽可能明确并确定预期的锁存器.使用注释、标签，并在可能的情况下使用 SystemVerilog always_latch.
    • case 语句应该有一个 default 条件.
    • if 语句应该有相应的 else.
    • 当组合逻辑块分配多个变量时，在块的开头(在任何case 或if 之前)给每个变量一个初始值.
    • case statements should have a default condition.
    • if statements should have a corresponding else.
    • When the combinatorial logic blocks is assigning many variables, giving each variable an initial value at the start of the block (before any case or if).
    • 组合逻辑的输入应该是触发器或组合逻辑的输出应该是触发器.
    • The inputs of combinatorial logic should be flops or the outputs combinatorial logic should be flops.
    • 代码审查要求审查者知道闩锁可以隐藏在哪里.
    • 使用 SystemVerilog 的 always_comb 可以帮助通过 linting 和逻辑等效性检查工具识别推断的锁存器.
    • Code review requires the reviewer(s) to know where latches could hide.
    • Using SystemVerilog's always_comb can help identify inferred latches with linting and logical-equivalency-checking tools.

    最坏的情况，将所有逻辑放在同步块中.所有推断的锁存器都变成推断的触发器.这通常是个坏主意，因为它会不必要地增加门数、创建更多布线并影响时序.

    Worst case scenario, put all logic inside synchronous blocks. All inferred latches become inferred flip-flops. This is usually a bad idea because it can unnecessarily increases the gate count, create more routing, and impact timing.

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