如何将固定分数应用于整数 [英] how can I apply fixed fraction to the integer

问题描述

我想乘以带有修改分数的整数，如下所示

I'd like to multiply to integer with modified fraction as following

(乘以幂级数负项求和)

我已经找到了将分数转换为 CSD 形式的方法.但我想知道如何申请乘以整数.

I have done what to find the method the fraction convert to CSD form. But I want to know how can I apply to multiply to integer.

例如，我得到了这个

然后我可以像这样作为 verilog rtl 表达式:

then I can get like this as verilog rtl expression :

但问题是，如果我得到的输入值为3，那么上面的代码如何计算?

But the problem is that what if I got the input value is 3, then how can I calculate above code?

但据我所知，它无法计算.因为3＞＞1是1，(3＞＞5)是0，(3＞＞7)是0，(3＞＞10)是0；

But As i know, It does impossible calculate. because 3>>1 is 1, (3>>5) is 0, (3>>7) is 0, (3>>10) is 0;

所以我无法得到正常的结果.找到修改后的分数表达式的原因也消失了.那么这个帖子的问题点是如何将修改后的分数应用于整数".

So I can't get the normal result. Also the reason of finding the modified fraction expression has gone away. Then this posting's question point is "how can I apply the modified fraction to the integer".

更新:这应该是这样的.y=((3<1024)>1)-((3<1024)>5)-((3<1024)>7)+((3<1024)>;<1024)>>10);

UPDATE : This should be like this. y= ((3<<1024)>>1) - ((3<<1024)>>5) - ((3<<1024)>>7) + ((3<<1024)>>10);

推荐答案

如果我们有 reg [3:0] 我们可以认为它可以容纳 0 到 15 的整数值.

If we have reg [3:0] we can consider that it can hold integer values 0 to 15.

现在我们想要小数信息，我们必须在知觉上添加小数位，但是verilog这个数字仍然是一个整数.

Now we want to have fractional information, we have to perceptually add fractional bits, but to verilog the number is still an integer.

我们仍然有 4 位，但我们改变了二进制加权，而不是 8 4 2 1 到 2 1 0.5 0.25.但是 verilog 不知道这一点，这完全取决于我们如何解释位模式.

We still have 4 bits, but we change the binary weighting, instead of 8 4 2 1 to 2 1 0.5 0.25. but verilog does not know this it is all about how we interpret the bit pattern.

在问题中，>>> 的右侧仅表示小数位.同样使用 T 表示 CSD 项中的 -1

In the question the right hand side of >> just represents the fractional bit. Also using T to represent a -1 in the CSD term

        2^-1 - 2^-5    - 2^-7      + 2^-10.
Decimal 0.5  - 0.03125 - 0.0078125 + 0.0009765625
Binary  0.1000T0T001

正如您所指出的，移动数字会导致截断为整数.诀窍是在执行此操作之前将小数位添加到数字中.

As you have noted shifting a number will result in truncating to an integer. The trick is to add fractional bits to the number before doing this.

例如向传入的整数添加 10 个小数位:

For instance to add 10 fractional bits to an incoming integer:

input [9:0] a,

wire [19:0] a_frac = { a, 10'b0};

记住 Verilog 认为这是一个整数，但我们必须以不同的方式解释这个数字.

Remember Verilog thinks this is an integer but we have have to interpret the number differently.

wire [19:0] y = (a_frac>>1) - (a_frac>>5) - (a_frac>>7) + (a_frac>>10);

y 现在应该包含一些内容，因为您为这些移动的值留出了空间.输出将有 10 个整数位和 10 个小数位.

y Should now contain something, as you left room for those shifted values. The output will have 10 Integer bits and 10 fractional bits.

要显示数字，您可以缩放实数:

To display the number you could scale a real:

$display("%d * 0.46194 = %f", a, y * 2.0**-10);

注意:我会避免将 x 作为 verilog 中的变量，因为 x 在 verilog 中具有特殊含义，要么不关心，要么是线路上的未知值.

NB: I would avoid x as a variable in verilog as x has a special meaning in verilog, either do not care or an unknown value on a wire.

EDA Playground 的一个简单示例.

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