Verilog 中的参数数组 [英] Parameter array in Verilog

问题描述

是否可以在 Verilog 中创建一个 parameter 数组?例如，以下内容:

Is it possible to create a parameter array in Verilog? For example, anything like the following:

parameter[TOTAL-1 : 0] PARAM_ARRAY = {1, 0, 0, 2}

如果不可能，有什么替代解决方案?

If it is not possible, what could be the alternative solution?

推荐答案

给定的示例是将解压缩的值分配给压缩的参数数组.这在 Verilog 中是不允许的.

The given example is assigning unpacked values to packed parameter array. This in not allowed with Verilog.

Verilog 仅支持基于简单向量的参数.它不支持解压缩的数组.取代 Verilog 的 SystemVerilog 确实支持参数数组.几乎所有现代 Verilog 模拟器都是真正的 SystemVerilog 模拟器(至少对于商业模拟器而言；开源模拟器支持不完整).要将文件读取为 SystemVerilog，请将 .v 的文件扩展名更改为 .sv.然后就可以将unpacked赋值给一个二维参数数组:

Verilog only support simple vector based parameters. It does not support unpacked arrays. SystemVerilog, which superseded Verilog, does support parameter arrays. Almost all modern Verilog simulators are really SystemVerilog simulators (at least for the commercial simulators; open source simulators have incomplete support). To have your files read as SystemVerilog, change the file extension for .v to .sv. Then you can assign unpacked to a 2 dimensional parameter array:

parameter [7:0] PARAM_ARRAY [TOTAL-1 : 0]   = {8'd1, 8'd0, 8'd0, 8'd2};

类型名称也是允许的.例如，使用 integer 创建一个 32x4 数组:

Type names are also allowed. For example, using integer to creates a 32x4 array:

parameter integer PARAM_ARRAY [TOTAL-1 : 0]   = {1, 0, 0, 2};

这记录在:

• IEEE Std 1364-2001 §3.11 参数
• IEEE Std 1364-2005 §4.10 参数
• (SystemVerilog) IEEE Std 1800-2012 §6.20 常量

• IEEE Std 1364-2001 § 3.11 Parameters
• IEEE Std 1364-2005 § 4.10 Parameters
• (SystemVerilog) IEEE Std 1800-2012 § 6.20 Constants

作为纯 Verilog 解决方案，您需要创建一个长向量:

As a pure Verilog solution, you will need to created one long vector:

parameter [8*TOTAL-1:0] PARAM_ARRAY = {8'd1, 8'd0, 8'd0, 8'd2};

然后使用硬编码的切片访问 PARAM_ARRAY[7:0] 或使用 +:: PARAM_ARRAY[8*index +: 8].请注意，+: 需要 Verilog-2001 或更高版本(即使是大多数开源模拟器都支持).使用 + 索引向量和数组:

Then access with a slice as hard coded PARAM_ARRAY[7:0] or using the +:: PARAM_ARRAY[8*index +: 8]. Note that +: requires Verilog-2001 or higher (which even most open-source simulators support). Indexing vectors and arrays with +:

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