Verilog 中的 == 和 === 有什么区别? [英] What is the difference between == and === in Verilog?

问题描述

有什么区别:

if (dataoutput[7:0] == 8'bx) begin

和

if (dataoutput[7:0] === 8'bx) begin 

执行dataoutput = 52'bx后，第二个给1，第一个给0，为什么?(0 或 1 为比较结果.)

After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.)

推荐答案

Verilog 中的某些数据类型，例如 reg，是 4-state.这意味着每个位可以是 4 个值之一:0,1,x,z.

Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z.

使用大小写相等"运算符，===，比较x，结果为1.

With the "case equality" operator, ===, x's are compared, and the result is 1.

使用==，比较的结果不是0，正如你所说；相反，结果是 x，根据 IEEE Std (1800-2009)，第 11.4.5 节相等运算符":

With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators":

对于逻辑相等和逻辑不等式运算符(== 和 !=)，如果，由于未知或高阻抗位在操作数中，关系是模棱两可，那么结果应该是1 位未知值 (x).

For the logical equality and logical inequality operators (== and !=), if, due to unknown or high-impedance bits in the operands, the relation is ambiguous, then the result shall be a 1-bit unknown value (x).

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