Verilog 中 = 和 <= 的区别是什么? [英] What is the difference between = and <= in Verilog?
问题描述
这段代码中 = 和 <= 有什么区别?另外，如何打印 data 的值?
What is the difference between = and <= in this code? Also, how do I print the value of data?
module always_example();
reg clk,reset,enable,q_in,data;
always @ (posedge clk)
if (reset) begin
data <= 0;
end else if (enable) begin
data <= q_in;
end
// if i put $print("data=%d", data); there is error
endmodule
推荐答案
<= 是一个非阻塞赋值.它用于描述顺序逻辑，就像在您的代码示例中一样.请参阅 IEEE Std 1800-2012，第 10.4.2 节非阻塞程序分配".
<= is a nonblocking assignment. It is used to describe sequential logic, like in your code example. Refer to IEEE Std 1800-2012, section 10.4.2 "Nonblocking procedural assignments".
= 用于阻塞赋值.用于描述组合逻辑.
= is for blocking assignments. It is used to describe combinational logic.
另见 Verilog Synthesis 中的非阻塞赋值，致命的编码风格！
您可以使用 $display 而不是 $print 来打印变量的值.另请参阅 IEEE Std 1800-2012，第 21.2 节显示系统任务".
You can use $display instead of $print to print the value of variables. See also IEEE Std 1800-2012, section 21.2 "Display system tasks".
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