Verilog 预处理器字符串连接 [英] Verilog preprocessor string concatenation

问题描述

我试图在 Altera Quartus 中使用 Verilog 预处理器宏，需要在变量名中使用参数值.

I am trying to use a Verilog preprocessor macro in Altera Quartus requiring use of a parameter value inside a variable name.

示例:

`define INCREMENT_COUNTER(parsername) \
__parsername_counter <= __parsername_counter + 4'h1;

所以使用 `INCREMENT_COUNTER(p1) 应该给

__p1_counter <= __p1_counter + 4'h1;

但是解析器名称没有正确替换并返回

However parsername is not properly replaced and returns

__parsername_counter <= __parsername_counter + 4'h1;

我也试过使用

__``parsername``_counter <= __``parsername``_counter + 4'h1;

这也不起作用.任何帮助将不胜感激.

which doesn't work either. Any help would be appreciated.

推荐答案

`` 适用于 VCS 和 Incisive，但我不了解 Quartus:

`` works in VCS and Incisive, but I don't know about Quartus:

module tb;

reg clk = 0;
always #5 clk = ~clk;

reg [3:0] __foo_counter = 0;

`define INC_CNT(name) __``name``_counter <= __``name``_counter + 1;

always @(posedge clk) `INC_CNT(foo)

initial begin
    $monitor($time, " clk=%b cnt=%d", clk, __foo_counter);
    #55 $finish;
end

endmodule

/*

Outputs:

                   0 clk=0 cnt= 0
                   5 clk=1 cnt= 1
                  10 clk=0 cnt= 1
                  15 clk=1 cnt= 2
                  20 clk=0 cnt= 2
                  25 clk=1 cnt= 3
                  30 clk=0 cnt= 3
                  35 clk=1 cnt= 4
                  40 clk=0 cnt= 4
                  45 clk=1 cnt= 5
                  50 clk=0 cnt= 5
*/

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