为什么这是一个格式错误的陈述? [英] Why is this a malformed statement?

问题描述

`timescale 1ps/1ps
module test1(output t1, input t2, input t3);
   always begin
        #1 or U_t1(t1, t2, t3);
   end
endmodule

我希望它或"t2 和 t3 并将其存储在 t1 中，延迟为 1ps，但我收到了格式错误的语句"错误.

I wanted this to "or" t2 and t3 and store it in t1 with a 1ps delay, but I am getting a "malformed statement" error.

推荐答案

请参阅 IEEE Std 1800-2012，第 28 节.门级和开关级建模，了解实例化一个门有延迟.always 块不应该这样使用.以下将在输出上添加 1ps 延迟:

Refer to IEEE Std 1800-2012, section 28. Gate-level and switch-level modeling for the proper syntax of instantiating a gate with a delay. An always block should not be used this way. The following will add a 1ps delay on the output:

`timescale 1ps/1ps
module test1(output t1, input t2, input t3);
    or #1 U_t1 (t1, t2, t3);
endmodule

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