为什么这个 verilog 关系语句返回 true? [英] Why is this verilog relational statement returning true?

问题描述

我有一个名为 sin_hall2 的 9 位有符号线.

I have a 9 bit signed wire called sin_hall2.

此语句返回 true.sin_hall2[8:0]>9'd1.

This statement returns true. sin_hall2[8:0]>9'd1.

当我查看我的模拟时，sin_hall2=-169.我假设这是 verilog 处理比较负数的方式，但我做错了什么.当我执行 sin_hall2[8:0]>9'sh001 时，我收到相同的结果.

When I look at my simulation, sin_hall2=-169. I am assuming it is the way verilog deals with comparing negative numbers, but what am I doing wrong. I receive the same result when I do sin_hall2[8:0]>9'sh001.

推荐答案

有符号数使用二进制补码格式.也就是说，如果解释为无符号，它们将显示为大数，即无符号数范围的后半部分.

Signed numbers use the twos-complement format. that is if interpreted as unsigned they will appear as large numbers, the second half of the unsigned number range.

如果比较的任何部分是无符号的，则比较是无符号的.选择位宽，即使整个范围都是无符号的

If any section of a comparison is unsigned then the comparison is unsigned. Selecting bit widths, even if the whole range, is unsigned

reg signed [8:0] sin_hall2;

initial begin
  sin_hall2 = -9'd169 ;
  $display( "Comparison unsigned : %b ", sin_hall2 > 9'd1 );
  $display( "Comparison cast     : %b ", sin_hall2 > $signed(9'd1) );
  $display( "Comparison signed   : %b ", sin_hall2 > 9'sd1 );
  $display( "Comparison signed [8:0]: %b ", sin_hall2[8:0] > 9'sd1 );
end

返回:

# Comparison unsigned : 1 
# Comparison cast     : 0 
# Comparison signed   : 0
# Comparison signed [8:0]: 1 

EDA Playground 示例.

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