Verilog 最佳实践 - 增加变量 [英] Verilog Best Practice - Incrementing a variable

问题描述

我绝不是 Verilog 专家，我想知道是否有人知道这些增加值的方法中哪种更好.抱歉，这个问题太简单了.

I'm by no means a Verilog expert, and I was wondering if someone knew which of these ways to increment a value was better. Sorry if this is too simple a question.

方式 A:

在组合逻辑块中，可能在状态机中:

In a combinational logic block, probably in a state machine:

//some condition
count_next = count + 1;

然后在顺序块中的某处:

And then somewhere in a sequential block:

count <= count_next;

或者方式B:
组合块:

Or Way B:
Combinational block:

//some condition
count_en = 1;

顺序块:

if (count_en == 1)
  count <= count + 1;

我经常看到方式 A.方式 B 的一个潜在好处是，如果您在状态机的许多地方增加相同的变量，它可能只使用一个加法器而不是多个加法器；还是那是假的?

I have seen Way A more often. One potential benefit of Way B is that if you are incrementing the same variable in many places in your state machine, perhaps it would use only one adder instead of many; or is that false?

哪种方法更受欢迎，为什么?是否有明显的缺点?

Which method is preferred and why? Do either have a significant drawback?

谢谢.

推荐答案

方式 B 的一个潜在好处是，如果您在状态机中的许多地方增加相同的变量，它可能只使用一个加法器而不是多个加法器；还是那是假的?

One potential benefit of Way B is that if you are incrementing the same variable in many places in your state machine, perhaps it would use only one adder instead of many; or is that false?

任何综合工具都会尝试自动资源共享.他们做得如何取决于所编写的工具和代码.这是一个描述设计编译器的一些功能的文档.请注意，在某些情况下，面积越小意味着时间越差.

Any synthesis tool will attempt automatic resource sharing. How well they do so depends on the tool and code written. Here is a document that describes some features of Design Compiler. Notice that in some cases, less area means worse timing.

哪种方法更受欢迎，为什么?是否有明显的缺点?

Which method is preferred and why? Do either have a significant drawback?

这取决于.Verilog(用于综合)是一种实现某些逻辑电路的方法，但规范并未具体说明如何实现.方式A可能与FPGA上的方式B相同，但由于无条件顺序分配，方式A与ASIC上的低功耗设计不一致.使用复位网络几乎是 ASIC 的一项要求，但由于许多 FPGA 以已知状态开始，您可以通过不使用它们来节省相当多的资源.

It depends. Verilog(for synthesis) is a means to implement some logic circuit but the spec does not specify exactly how this is done. Way A may be the same as Way B on an FPGA but Way A is not consistent with low power design on an ASIC due to the unconditional sequential assignment. Using reset nets is almost a requirement on an ASIC but since many FPGAs start in a known state, you can save quite a bit of resources by not having them.

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