从测试平台访问子模块中的输入和输出 [英] Accessing inputs and outputs in sub-modules from testbench

问题描述

我的被测设备 (DUT) 有许多子模块，我想测试其中的一些.

My device-under-test (DUT) has many sub-modules and I would like to test some of them.

我的测试装置将是我项目的顶层——比 DUT 高一层——而且由于我似乎只能访问低一层的模块的输入和输出，我只能访问顶层输入和 DUT 的输出.

My test fixture will be the top level of my project - one level higher than the DUT - and since I can only seem to access the inputs and outputs of the modules one level down, I can only access the top-level inputs and outputs of the DUT.

我希望能够访问来自测试夹具下方两层或更多层的模块的信号，理想情况下无需重写任何模块来添加更多输出，这样我想要测试的信号就可以连接到顶层.

I would like to be able to access signals from the modules two or more levels beneath the test fixture, ideally without having to rewrite any modules to add more outputs so the signals I want to test are connected to the top level.

我可以重写被测设备，但这似乎很耗时，我觉得应该有一个更快的方法.

I could rewrite the device under test but this seems time-consuming and I feel there should be a quicker way.

有没有办法编写一个可以访问子模块内信号的测试装置，而无需重写 DUT?

推荐答案

如果您只需要监视顶级dut 模块内的信号，您可以使用分层路径说明符将范围缩小到dut:

If you only need to monitor signals inside your top-level dut module, you can use hierarchical path specifiers to scope down into the dut:

dut.read_data

SystemVerilog 还提供了 bind 语句来做类似的事情.

SystemVerilog also offers the bind statement to do something similar.

如果您需要驱动内部dut信号，您应该为子模块创建一个单独的测试平台.这更耗时，但可以为您提供更好的控制并让您实现 100% 的覆盖率(有时在顶层可能很困难).

If you need to drive internal dut signals, you should create a separate testbench for the sub-module. This is more time-consuming, but gives you better control and allows you to achieve 100% coverage (which can sometimes be difficult at the top-level).

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