verilog 中的整数输入端口类似于 vhdl? [英] Integer input ports in verilog similar to vhdl?

问题描述

我是 verilog 的新手.我使用 vhdl 中的整数输入和输出构建了我的代码.现在我想在 verilog 中构造相同的代码.但是我开始知道 verilog 中的输入端口不能是整数类型.可以做什么.我更喜欢可综合的答案.

I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would prefer an answer which is synthesizable.

vhdl 代码:

LIBRARY ieee;
USE ieee.All;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY adder_5 IS
PORT (
 a : IN integer ;
 b : IN integer; 
 c : OUT integer 
);

END adder_5;
ARCHITECTURE add OF adder_5 IS
BEGIN
 c<= (a rem 32) + (b rem 32);
END add;

推荐答案

Verilog 中的整数和 VHDL 中的整数不是一回事.在 VHDL 中，整数是至少 32 位的带符号 2 状态 类型.在 Verilog 中，整数是一个 32 位有符号 4 状态 变量.所以，在 Verilog 中，

Integers in Verilog and integers in VHDL are not the same thing. In VHDL an integer is a signed 2-state type with at least 32 bits. In Verilog an integer is a 32-bit signed 4-state variable. So, in Verilog,

integer a;

和

reg signed [31:0] a;

是等价的.在 Verilog 中，输入端口必须是网络类型，因此不允许整数输入端口.但是，允许输出端口是变量，因此输出端口可以是整数.所以，你可以用 reg signed [31:0] 替换 VHDL 输入整数，用 integer 输出整数，你在 Verilog 中的代码是

are equivalent. In Verilog input ports had to be net types, so integer input ports were not allowed. However, output ports were allowed to be variables, so an output port could be an integer. So, you can replace VHDL input integers with reg signed [31:0] and output integers with integer and your code in Verilog is

module adder (input wire signed [31:0] a, b, output integer c);

  always @(*)
    c = a%32 + b%32;

endmodule

或者也许是为了一致性:

or perhaps for consistancy:

module adder (input wire signed [31:0] a, b, output reg signed [31:0] c);

http://www.edaplayground.com/x/5PZe

因此，输出端口允许整数，但输入端口不允许.

So, integers were allowed in output ports but not input ports.

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