防止编译器优化逻辑 [英] Prevent compiler from optimizing logic away

问题描述

我想生成一个持续很短时间的reset 信号(高电平有效).我通过以下代码实现了它:

I'd like to generate a reset signal (active high) that will last for a short period of time. I achieved it by following code:

always @(posedge clk or negedge rst_n or posedge data) begin
  if(~rst_n | data)
    data <= 1'b0;
  else if(ena)
    data <= 1'b1;
  else
    data <= data;
end 

合成为D触发器:

我生成的信号只有 1 的时间等于通过 OR 门的传播时间.现在我想删除 rst_n 信号.但是如果我这样做，我会收到以下 D 触发器:

My generated signal will be 1 only for time equal to propagation time through OR gate. Now I want to remove rst_n signal. But if I do that, I receive the following D flip-flop:

那样的话，我的信号永远不会高.我想出的最简单的解决方法是在 Q 和 CLR 之间添加 2 个 NOT 门.不幸的是，我的软件(Quartus II)会将这两个门综合起来.

In that case, my signal will never be high. The easiest way to solve that I came up with is to add 2 NOT gates between Q and CLR. Unfortunately, my software (Quartus II) will synthesize those two gates away.

tl;dr - 如何删除 rst_n 以便正确生成 reset 信号?

tl;dr - how to remove rst_n so reset signal will be generated correctly?

推荐答案

您是否尝试使用 Quartus 的synthesis keep"标签插入缓冲区?

Did you try using the "synthesis keep" tag for Quartus to insert buffers?

http://quartushelp.altera.com/13.1/mergedProjects/hdl/vlog/vlog_file_dir_keep.htm

试试这个:

module test(clk,ena,data);
input clk, ena;
wire data_n /*synthesis keep*/;
wire data_nn /*synthesis keep*/;
output reg data;

assign data_n = ~data; 
assign data_nn = ~data_n; 

always @(posedge clk or posedge data_nn) begin
  if(data_nn)
    data <= 1'b0;
  else if(ena)
    data <= 1'b1;
  else
    data <= data;
end

endmodule

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