“生成"附近的语法错误和“endgenerate"在verilog中 [英] Syntax error near "generate" and "endgenerate" in verilog

问题描述

我是 Verilog 的新手，我正在尝试使用 verilog 实现单精度浮点加减法.我收到一个我无法纠正的错误.谁能帮帮我吗?

I am new in Verilog and I am trying to implement single precision floating point addition-subtraction using verilog. I am getting an error which I am unable to correct. Can anyone please help me?

module addModule(Rs,Re,Rm,As,Ae,Am,Bs,Be,Bm);

module addModule(Rs,Re,Rm,As,Ae,Am,Bs,Be,Bm);

//Declarations of ports
  Rs,Re,Rm;
  As,Bs;
  input [7:0] Ae,Be;
  input [22:0] Am,Bm;

reg [7:0] Re;
reg [22:0] Rm;
reg Rs;
//wire declarations.
wire [23:-1] C;
assign C[-1] = 0;
wire [23:1] sum;
//variable declaration.
genvar count;

always @(*)
begin
//Add two mantissas.
if ((As^Bs)==0)
    begin
        generate   //getting error here "Syntax error near "generate"."
        for(count=0;count<24;count=count+1)
            begin
                add add_1(.c_out(C[count]),.sum(sum[count]),.in1(tempAm[count]),.in2(tempBm[count]),.c_in(C[count-1]));
            end
        endgenerate   //syntax error near "endgenerate"
    end

else
    begin
        generate   //Syntax error near "generate".
        for(count=0;count<24;count=count+1)
            begin
                subtract sub_1(.c_out(C[count]),.dif(sum[count]),.in1(tempAm[count]),.in2(tempBm[count]),.c_in(C[count]));
            end
        endgenerate   //Syntax error near "endgenerate".
    end


end
endmodule

提前致谢.:)

推荐答案

在 Verilog 中，当您实例化一个模块时，这意味着您正在向模块添加额外的硬件板.

In Verilog, when you are instantiating a module, that means you are adding extra hardware to the board.

必须在模拟开始之前(即在编译时)添加此硬件.在这里，您可以不在每个时钟脉冲上添加/删除硬件.

This hardware must be added before simulation starts(i.e. at compile time). Here, you can not add/remove hardware at each clock pulse.

一旦实例化，就会针对每个时间戳的模拟执行/检查模块，直到结束.

Once instantiated, the module is executed/checked for each timestamp of simulation, till the end.

因此要执行任何模块，只需将其实例化，为其提供 clk 和其他所需的输入，然后在子模块本身中添加 always 块.

So to execute any module, just instantiate it, providing the clk and other required inputs to it, and add the always block in the sub-module itself.

一旦硬件被实例化，它将根据其内部的逻辑执行，整个生命周期.

Once the hardware is instantiated, it shall be executed according to the logic inside it, for entire life time.

在这里，您在错误的地方实例化模块.generate 块的使用必须在任何程序块之外完成.

Here you are instantiating module at wrong place. The use of generate block must be done outside any procedural blocks.

// generate outside any other blocks
   generate   
    for(count=0;count<24;count=count+1)
        begin
            add add_1(.c_out(C[count]),.sum(sum[count]),.in1(tempAm[count]),.in2(tempBm[count]),.c_in(C[count-1]));
        end
    endgenerate

always @(*)
begin
// Other stuff here.
end

如果您想操作sub_1模块的输入信号，只需操作C、sum和addModule 模块中声明的其他变量.由于它们是连接的，因此更改也应反映在 subtract sub_1 模块中.

If you want to manipulate input signals of the subtract sub_1 module, simply manipulate C,sum and other variables declared in addModule module. Since they are connected, the change shall reflect in subtract sub_1 module too.

有关生成块的更多信息，请参阅模块实例化，生成块示例 和 类似问题链接.

For more information on generate block, refer Module Instantiation, Generate block example and a similar question links.

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