Altera Quartus 错误 (12007):顶层设计实体“alt_ex_1"未定义 [英] Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined

问题描述

我已经查看了之前的所有问题，似乎没有人有问题和我的一样简单.我也在网上搜索过，但找不到解决方案.

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution.

我是 VHDL 的新手，正在尝试编译提供的简单示例由 Altera 提供，内容如下:

I'm new to VHDL and am trying to compile the simple example provided by Altera, which is as follows:

library ieee;
use ieee.std_logic_1164.all;

entity light is
port(x1, x2: in std_logic;
          f: out std_logic);
end light;

architecture LogicFunction of light is
begin
    f <= (x1 and not x2) or (not x1  and x2);
end LogicFunction;

我遵循了 Altera 教程,但是当我尝试编译项目时出现错误:

I followed the project creation steps in the Altera tutorial, but when I try to compile the project I get the error:

Error (12007): Top-level design entity "alt_ex_1" is undefined

推荐答案

在 Starting a New Project 一章中，你被要求调用你的项目 light.在我看来，您没有正确执行该步骤并将项目命名为 alt_ex_1.这就是您收到 12007 错误的原因，因为编译器不知道您设计中的顶级实体是什么.

In chapter Starting a New Project, you were asked to call your project light. It seems to me that you didn't follow that step correctly and name your project alt_ex_1. That's why you're getting 12007 error, since the compiler has no idea what is the top-level entity in you design.

要解决该问题，您可以:

To solve that problem you can:

1. 更改Assignments -> 中的顶级实体分配设备 ->一般.
2. 通过 Project Navigator 将您的模块设置为顶级实体(Files -> Set as top-level entity).

1. Change the top-level entity assignment in Assignments -> Device -> General.
2. Set your module as top-entity via Project Navigator (Files -> Set as top-level entity).

顺便说一句1、2、3、... - 都差不多问题.

Btw 1, 2, 3, ... - all about the same problem.

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