Delta 周期和波形 [英] Delta Cycles and Waveforms
问题描述
谁能解释增量周期如何影响 VHDL 模拟的波形?我知道这与 VHDL 如何确定优先级有关，但我不确定如何确定.
你不会在 VHDL 标准 (IEEE Std 1076-2008) 中找到信息，并且 delta 周期的作用没有被广泛理解(这里有一个提示关于作为语言用户您实际需要了解多少，抽象知识就足够了).
Delta 周期先于 VHDL.您可以在 Internet 上找到可追溯到 1971 年的参考资料. VHDL 从 CONLAN BCL 时间模型中获取它的 delta 周期，在该模型中它们被称为步骤(注意，我们今天看到了交互式模拟器命令来步进，请参阅关于 VHDL 的 Delta 延迟的起源, SUMIT GHOSH, Int. J. Engng Ed. Vol. 20, No. 4, pp. 638-645, 2004, and CONLAN Report, R. Piloty, M. Barbacci,D. Borrione、D. Dietmeyer、F. Hill、P. Skelly，Springer-Verlag 1983).
Ishiura Nagisa 的博士论文中有一个简单的参考资料解释了这个概念
一个单位时间，不关注单位时间内的计算顺序.实际上，阶跃或Δ-延迟与单位延迟模型下的仿真相关联.在某些情况下，最终结果取决于计算顺序.例如，在图 7.2 中，虽然电路不切实际，但 D 上可能存在风险，从而改变 Q 上的信号值.通过使用 bcl 和 VHDL 模型，我们永远不会得到这个结果.这又是因为这些语言是基于确定性计算模型.
这个不是很清楚.连续增量周期内的执行顺序由当前仿真时间的信号更新决定.Delta 周期将按确定的顺序发生.
作者继续阐述了作为替代方案的非确定性行为模型的优点，这里剩下的叙述与 VHDL 几乎没有关系.
除了图 7.2 所示的完全理论模型的非确定性之外.VHDL 无法处理零延迟反馈回路.为了捕捉这些情况，VHDL 仿真器实现了仿真停止前允许的最大增量周期数.虽然这个数字有时可以通过命令行选项设置，但 [Coe89] 参考(VHDL 手册，Vantage Analysis Systems 的 David R. Coelho 于 1989 年撰写)正处于作者模拟器开始出现的时代delta 周期最大值为 127，反映了更简单的模型，并且肯定会随着时间的推移而增加.在现代模拟器中，默认最大值通常为 5,000 或 10,000，反映模型的复杂性.这个想法是允许足够的增量循环来克服模型复杂性，而不会让零延迟循环肆无忌惮地运行.
在图 7.2 中，如果 A、B、C 和 D 是 VHDL 中的信号，其中反相器、缓冲器和与门代表具有一个增量延迟(零延迟模型)的信号分配，则信号 D 将没有单个增量周期脉冲(小故障，小于可测量的时间).如果你想要一个脉冲，你需要延迟，依靠逆变器和缓冲器的下降时间不同.
当使用 0 延迟建模时，VHDL 可能需要额外的信号作为缓冲器来提供增量延迟或补偿由于逻辑路径中不同数量的信号分配而具有增量延迟的信号.另一方面，综合忽略了延迟(除了偶尔提供警告的工具).
因此，使用信号更新的增量周期为零延迟模型提供了确定性 - 基于所有进程暂停后发生的信号更新的正确结果.如果没有这种确定性，您将依赖于变量的使用顺序.使用信号可以让您在任意边界上分解设计.可以不考虑它们之间的顺序来描述进程和其他并发语句.
优先级在标准中有特定的含义(运算符优先级)，说确定性"更安全.您每次都会得到相同的答案，因为即使是零延迟分配，信号更新也不会在流程执行期间发生.
Can anyone explain how delta cycles affect waveforms simulated by VHDL? I understand that it has to do with how VHDL determines precedence but I'm not exactly sure how.
You won't find the information in the VHDL standard (IEEE Std 1076-2008), and what delta cycles do are not widely understood (there's a hint here about how much you actually need to know as a language user, an abstract knowledge can suffice).
Delta cycles precede VHDL. You can find references on the Internet dating back to 1971. VHDL gets it's delta cycles from the CONLAN BCL Time model where they are called steps (note we see interactive simulator commands to step today, see On the Origin of VHDL's Delta Delays, SUMIT GHOSH, Int. J. Engng Ed. Vol. 20, No. 4, pp. 638-645, 2004, and CONLAN Report, R. Piloty, M. Barbacci, D. Borrione, D. Dietmeyer, F. Hill, P. Skelly, Springer-Verlag 1983).
There's a simple reference explaining the concept in Ishiura Nagisa's PhD dissertation Studies on Logic Simulation and Hardware Description Languages where in Chapter 7 describing NES: A Nondeterministic Behavior Model for Hardware Description Languages.
7.2.2 Modeling of a Zero Delay
In designing hardware, timing relations among events are very important. HDL's must have a framework of specification of timing relations. Thus one of the most important issues in developing a behavioral model of hardware is how to model time.
Probably one of the simplest way of modeling time is to represent a waveform by a sequence of symbols, each of which is associated with a minimum unit of the discrete time.
In VHDL terms these symbols are values of a type and discrete time is represented by a value of simulation time.
... Then the behavior of a hardware component is represented by a sequential machine over the set of the symbols. Although this modeling realizes simple mathematical handling, it lacks the ability to express the occurrence of multiple events at the same place within a unit time. So it is very difficult to explain the behavior of the circuits that contain loops consisting of zero delay components.
Simulating VHDL models produce a sequence of waveform events over simulation time. VHDL actually won't handle feedback loops with zero delay components at all. The point of Chapter 7 is to describe how to do so with an alternative HDL.
... Here, zero delay means the delay less than the unit time. It is a product of the quantitization of time. If the delay time of a component is less than the minimum unit of the time, it is specified as 0. The zero delay also comes up when we take a clock cycle as a unit time. In such a case, delay of gates is treated as zero delay because it is not measured by the unit time. The zero delay expresses before-after relationship or causality whose delay time is 0 measured by the unit time,
In VHDL simulation cycles that occur without the advancement of simulation time are delta cycles resulting from signal assignments with default incremental delays of 0. We can see that Jayaram Bhasker's description of delta cycles in A VHDL Primer (AT&T) is influenced by this passage. A VHDL Primer's description of delta cycles is widely quoted and still not enlightening, resulting in a search for writings of computer scientists on the subject.
Note that VHDL models operate by the resumption and subsequent re-suspension of processes in wait statements (a process with a sensitivity list has an implicit wait statement with the sensitivity list, as a the last statement of the process). Order of process execution resumption is not specified, VHDL can be simulated with processes running in parallel.
To deal with this signal updates are scheduled and don't take effect until all processes have suspended. If there are any updates scheduled for the current simulation time, the next simulation cycle is a delta cycle, otherwise simulation time is advanced to the next time a scheduled signal update occurs for the next simulation cycle. When there are no further events scheduled, simulation time advances to time'HIGH and simulation ends.
These delta cycles allow determinism in model execution where processes can execute in parallel by using signals that have history. Signals don't change during process execution, every process will execute identically every time. VHDL is formal notation intended to support formal verification of it's synthesis eligible subset, determinism is important here.
In order to deal with the zero delay, the time models of bcl (Conlan)[Pi183] and VHDL [Coe89] are designed on the basis of a sub-unit time named a step and a Δ-delay, respectively. The signal value at a unit time is the final result of the infinite repetition of the computation in a step or a Δ-delay. Since these models are invented to compute the final result at
a unit time, no attention is paid to the order of the computation within a unit time. Actually, a step or a Δ-delay is associated with simulation under the unit delay model. There are cases where the final result depends on the order of the computation. For example, in Fig. 7.2, while the circuit is impractical, there may be a hazard on D which changes the signal value on Q. By using the models of bcl and VHDL, we will never get this result. This is again because these languages are based on the deterministic computation model.
This is not quite clear. Order of execution within successive delta cycles is determined by signal updates to the current simulation time. Delta cycles will occur in deterministic order.
The author goes on to expound the virtues of a nondeterministic behavioral model as an alternative and the remaining narrative here has little bearing on VHDL.
In addition to the non-determinism of the wholly theoretical model shown in Figure 7.2. VHDL can't deal with zero delay feedback loops. To catch these cases VHDL simulators implement a maximum number of delta cycles that are allowed before being simulation is stopped. While this number can sometimes be set via a command line option the [Coe89] reference (The VHDL Handbook by David R. Coelho of Vantage Analysis Systems in 1989) was in an era when the author's simulator started out with a delta cycle maximum of 127, reflecting simpler models and is bound to have increased over time. In modern simulators the default maximum is usually either 5,000 or 10,000 reflecting model complexity. The idea is to allow enough delta cycles to overcome model complexity without letting zero delay loops to run unbridled.
In Figure 7.2 if A, B, C and D are signals in VHDL where the inverter, buffer, and AND gate represent signal assignments with one delta delay (zero delay models), Signal D will not have a single delta cycle pulse (a glitch, smaller than measurable time). If you want a pulse you need delays, counting on the different in fall through times for the inverter and buffer.
When modeling with 0 delays VHDL can require additional signals as buffers to give delta delays or compensate for signals that have delta delays due to a different number of signal assignments in the logic path. On the other hand delays are ignored by synthesis (other than the occasional tool providing warnings).
So delta cycles using signal updates provide determinism for zero delay models - the correct results based on signal updates occurring after all processes are suspended. Without that determinism you'd be depending on order of assignment as in the use of variables. Using signals allows you to break up designs on arbitrary boundaries. Processes and other concurrent statements can be described without regard to order between them.
Precedence has a specific meaning in the standard (operator precedence), it's safer to say 'determinism'. You get the same answer every time because signal updates don't occur during process execution even for zero delay assignments.
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