如何在 VHDL 中将 8 位转换为 16 位? [英] How to convert 8 bits to 16 bits in VHDL?

问题描述

我有一个来自 ADC 转换器的 8 位输入信号 (std_logic_vector(7 downto 0)).我必须将它们转换为 16 位信号 (std_logic_vector(15 downto 0))，以便将 16 位信号处理到 16 位系统.

I have an input signal from ADC convertor that is 8 bits (std_logic_vector(7 downto 0)). I have to convert them to a 16 bits signal (std_logic_vector(15 downto 0)) for 16 bits signal processing to the 16 bits system.

推荐答案

如果将 8 位值解释为有符号的(2 的补码)，那么一般和标准的 VHDL 转换方法是使用 IEEE numeric_std 库:

If the 8 bit value is interpreted as signed (2's complement), then the general and standard VHDL conversion method is to use the IEEE numeric_std library:

library ieee;
use ieee.numeric_std.all;

architecture sim of tb is
    signal slv_8  : std_logic_vector( 8 - 1 downto 0);
    signal slv_16 : std_logic_vector(16 - 1 downto 0);
begin
    slv_16 <= std_logic_vector(resize(signed(slv_8), slv_16'length));
end architecture;

因此首先将 std_logic_vector 转换为有符号值，然后应用调整大小，这将对有符号值进行符号扩展，最后将结果转换回 std_logic_vector.

So first the std_logic_vector is converted to a signed value, then the resize is applied, which will sign extend the signed value, and the result is finally converted back to std_logic_vector.

转换相当冗长，但具有通用性的优点，即使稍后更改目标长度也能正常工作.

The conversion is rather lengthy, but has the advantage that it is general and works even if the target length is changed later on.

属性 'length 只返回 slv_16 std_logic_vector 的长度，即 16.

The attribute 'length simply returns the length of the slv_16 std_logic_vector, thus 16.

对于无符号表示而不是有符号，可以使用 unsigned 而不是 signed 来完成，因此使用此代码:

For unsigned representation instead of signed, it can be done using unsigned instead of signed, thus with this code:

    slv_16 <= std_logic_vector(resize(unsigned(slv_8), slv_16'length));

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