使用通用参数作为端口数组长度 [英] Use generic parameter as port array length

问题描述

我想做什么:

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
      -- ...
      h : in array(0 to NTAPS-1) of std_logic_vector(15 downto 0) );
end FIRfitler;

但是带有 h 的那一行的语法不正确.

But the syntax on the line with h is not correct.

这个问题类似:如何指定一个整数数组在 VHDL 中是通用的? 但这并不能让我在实例化时获得通用的抽头数.这甚至可能吗?

This question is similar: How to specify an integer array as generic in VHDL? But that doesn't get me the generic number of taps when instantiating. Is this even possible?

推荐答案

如果你在包中声明了一个不受约束的数组类型，那么你可以基于一个泛型来约束该数组，如下代码所示:

If you declare an unconstrained array type in a package, then you can constrain the array based on a generic, as shown in the code below:

library ieee; use ieee.std_logic_1164.all;

package FIRfilter_pkg is
  type x_t is array(natural range <>) of std_logic_vector(15 downto 0);
end package;


library ieee; use ieee.std_logic_1164.all;
library work; use work.FIRfilter_pkg.all;

entity FIRfilter is
   generic (
      NTAPS : integer );
   port (
     x : in x_t(0 to NTAPS-1);
     z : out std_logic_vector(15 downto 0) );  -- For simple example below
end FIRfilter;


library ieee; use ieee.numeric_std.all;

architecture syn of FIRfilter is
begin
  z <= std_logic_vector(unsigned(x(0)) + unsigned(x(1)));  -- Usage example
end architecture;

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