读取 OUT 端口进行调试 [英] Reading OUT ports for debugging

问题描述

我有一个 FIFO，它的接口看起来像这样:

I have a FIFO which has an interface that looks something like this:

entity fifo is
    port (
    CLK               : IN  std_logic := '0';
    DIN               : IN  std_logic_vector(31 DOWNTO 0);
    ALMOST_EMPTY      : OUT std_logic;
    ALMOST_FULL       : OUT std_logic;
    DOUT              : OUT std_logic_vector(31 DOWNTO 0);
    ...
    WR_ACK            : OUT std_logic
);
end fifo;

这个接口是给定的，我不能改变.现在的事情是，出于调试目的，我想看看向/从 FIFO 写入和读取的内容.换句话说，理想情况下，我想分配两个调试 FIFO 的输入和输出值，即.

This interface is given and I can't change is. The thing is now, for debugging purposes, I wanna see what is written and read to/from the FIFO. In other words, ideally I would like to assign two debug the in and out values of the FIFO, ie.

  DBG_FIFO_IN  <= DIN;
  DBG_FIFO_OUT <= DOUT;

出于显而易见的原因，第二个作业给了我以下错误消息:

For obvious reasons, the second assignment gives me the following error message:

[exec] ERROR:HDLParsers:1401 - 无法读取模式 OUT 的对象 DOUT.

[exec] ERROR:HDLParsers:1401 - Object DOUT of mode OUT can not be read.

所以我想知道是否有任何方法可以将 DOUT 值分配给我的调试符号.接口给了，所以我不能让DOUT成为inout信号.

So I am wondering if there is any way how I can assing the DOUT value to my debug symbol. The interface is given, so I cant make DOUT an inout signal.

非常感谢有用的评论！

推荐答案

您必须将 fifo 输出分配给您可以读取的本地信号，然后将该信号分配给输出(或分配给它们)两者并行):

You have to assign the fifo output to a local signal you can read, then assign that signal to the output (or assign them both in parallel):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

或

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);

这篇关于读取 OUT 端口进行调试的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！