在 VHDL 中使用另一个文件中的实体 [英] Using entities from another file in VHDL

问题描述

如何从 VHDL 的工作区包含"另一个文件，然后使用在另一个文件中实现的实体的架构?这是我所拥有的，但这是不对的:

How does one "include" another file from a workspace in VHDL and then use an architecure of an entity that is implemented in another file? Here is what I have but it is not right:

更新代码:

library ieee;
use ieee.std_logic_1164.all;
library Part2;
use Part2.all;


entity problem4Gates is
    port(X,Clk: in std_logic; Q: out std_logic_vector(2 downto 0)) ;
end entity problem4Gates;  

architecture behavioral OF problem4Gates IS  

for all: yourGateName use entity  Part2.JKflipFlop(jkFF); --port (J, K, Clk, Preset, Clear : in std_logic; Q, Qn : Buffer std_logic) --JKflipFlop --jkFF    
signal s0, ns0, s1, ns1, s2, na2, ps0, ps1, ps2, restart : std_logic :='0';
begin
    process(clk)
    begin                  
         yourgatename( ns0, clk, '0', restart, Q(0), ns0 );
    end process;
end architecture behavioral;

我现在收到 2 个错误:

I now get 2 errors:

# Error: COMP96_0078: Part3.vhd : (13, 10): Unknown identifier "yourGateName".
# Error: COMP96_0134: Part3.vhd : (13, 10): Cannot find component declaration.

推荐答案

如何从 VHDL 的工作区包含"另一个文件，然后使用在另一个文件中实现的实体的架构?

How does one "include" another file from a workspace in VHDL and then use an architecure of an entity that is implemented in another file?

您没有包含文件".VHDL 不是 C.

You don't "include a file". VHDL is not C.

如果您编译一个特定实体的多个不同架构，它们可以都在一个文件中，甚至与实体在同一个文件中，也可以分散在多个文件中.

If you compile several different architectures of a particular entity they can all be in one file, even the same file as the entity, or they can be scattered across multiple files.

然后您可以使用它们 - 最简单的方法是直接实例化.在更高级别的架构中，您可以:

You can then make use of them - the easiest way is direct instantiation. In the higher-level architecture, you do:

inst_of_one_arch     : entity work.some_entity(one_arch) port map....
inst_of_another_arch : entity work.some_entity(another_arch) port map....

还有其他方法，但它们可能会很麻烦.

There are other ways, but they can be a lot of hassle.

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