触发器实现与过程.[VHDL] [英] Flip flop implementation with process. [VHDL]

问题描述

我的问题是关于以下代码:

My question is in regards to the following code:

library ieee;
use ieee.std_logic_1164.all;

entity exam is port (
    I,CLK,RESET : in std_logic;
    Q : out std_logic
);
end entity;

architecture exam_arc of exam is
    signal temp_sig : std_logic;
begin
    process (CLK,RESET)
    begin
        if RESET = '1' then
            temp_sig <='0';
        elsif CLK'event and CLK='1' then
            temp_sig <= I;
        end if;
        Q <= temp_sig;
    end process;
end exam_arc;

这段代码似乎模拟了一个在时钟上升沿运行的 D 触发器，但是这个问题的答案 [这个问题来自考试] 声称这个 D 触发器在时钟的下降沿运行时钟.

It seems that this piece of code simulates a D flip flop that operates on rising edge of the clock, however the answer [this question is taken from an exam] to this question claims that this D flip flop operates on falling edge of the clock.

这个 VHDL 代码模拟了什么样的触发器?

What kind of flip flop this VHDL code simulates?

推荐答案

这是一个棘手的问题.请注意，该过程会在时钟上升沿和下降沿上唤醒，并且中间信号 temp_sig 在上升沿上分配.

It's a trick question. Note that the process wakes up on both rising and falling clock edges, and that the intermediate signal temp_sig is assigned on the rising_edge.

将其与信号分配(延迟分配)的语义放在一起，看看你会得到什么.

Put that together with the semantics of signal assignment (postponed assignment) and see what you get.

按照吉姆的建议通过模拟进行交叉检查...

Cross check via simulation as Jim suggests...

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