一个简单的 VHDL 电路不会显示初始值 [英] A simple VHDL circuit won't display initial value

问题描述

这是我的代码，非常简单.我将在 Altera Cyclone II 板上循环显示字母表的前 8 个字母.

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board.

entity lettercycle is
    port(
        SW  : in  std_logic; -- toggle switch
        HEX0 : out std_logic_vector(6 downto 0) -- 7-segment display
        );
end lettercycle;

architecture behavioural of lettercycle is
    signal counter : integer range 0 to 7 := 0;
begin
    process
        type SEGMENT_ARRAY is array (0 to 7) of std_logic_vector(6 downto 0);
        variable SEVENSEG : SEGMENT_ARRAY := ("0001000","0000011","1000110","0100001","0000110","0001110","0010000","0001001");
        begin
        HEX0 <= SEVENSEG(counter);
        wait until SW = '0';
        counter <= counter + 1;
        end process;
end behavioural;

这很好用，它会循环，但最初它在我的七段显示器上不显示A".它显示8"(所以本质上什么都没有).一旦我按下逻辑 0 开关的 SW，它就会变为A"并正确地循环到B"、C"等.它也可以正确循环.它没有做的是最初设置为A".如果我强迫

This works great, it cycles but initially it doesn't display "A" on my seven segment display. It displays "8" (so nothing essentially). Once I push SW which is a logic 0 switch it changes to 'A' and cycles to 'B', 'C', etc properly. It also loops correctly. What it isn't doing is initially setting to 'A'. If I force

    HEX0 <= SEVENSEG(0);

然后它最初会显示A"，所以我没有想法.这可能与弹跳有关吗?

Then it will display 'A' initially so I'm out ideas. Could this be related to bouncing?

推荐答案

综合工具使用下降沿触发器实现该过程，作为wait until SW = '0'; 的结果，所以 counter 和 HEX0 里面进程在 SW 的下降沿更新(因此 HEX0 不是锁存器).

The synthesis tool implements the process with falling edge flip-flops, as a result of the wait until SW = '0';, so both the counter and HEX0 inside the process are updated at falling edge of SW (thus HEX0 is not a latch).

然而，综合工具不会传播 counter 的初始 0 值基于通过 SEVENSEG 映射到 HEX0 上的初始值，所以你不会在输出中看到初始的A".

The synthesis tool does however not propagate the initial 0 value of counter to initial value on HEX0 based on mapping through SEVENSEG, so you won't see an initial 'A' on the output.

合成输出如下图所示，其中触发器开启也可以看到输出.

The synthesis output is shown on the figure below, whereby the flip-flops on the output can also be seen.

通过更新进程和HEX0赋值给:

The intended operation is possible with update of process and HEX0 assign to:

process (SW) is
begin
  if falling_edge(SW) then
    counter <= counter + 1;
  end if;
end process;
HEX0    <= SEVENSEG(counter);

这也将删除 HEX0 输出上不必要的触发器.

This will also remove the unnecessary flip-flops on the output for HEX0.

请注意，SEVENSEG 已移至架构级别声明为常量.

Note the SEVENSEG is moved to architectural level declaration as constant.

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