VHDL 没有运算符“-"的函数声明； [英] VHDL No Function declaration for operator "-"

问题描述

所以我有一项任务是在 2 个向量之间进行模运算(这里称为红利和除数)，所以我需要的是红利模除数.我们对这段代码有一些限制，即不能使用iee_std_logic_1164、textio等.我认为唯一允许的库是IEEE和IEEE.numeric_bit

So i have a task to do the mod operation between 2 vectors(called here dividendo and divisor), so what i need is dividendo mod divisor. We have some restrictions on this code, that is, we cant use iee_std_logic_1164, textio, etc. I think the only libraries allowed are IEEE and IEEE.numeric_bit

这个操作的算法告诉我:

The algorithm to this operation tells me to:

while(dividendo >= divisor){
  dividendo = dividendo - divisor
 }
return dividendo

然后我写了这个 vhdl 文件:

And then i wrote this vhdl file:

 library IEEE;

entity resto is
port (clock , reset : in bit ;
    inicio : in bit ;
    fim : out bit ;
    dividendo , divisor : in bit_vector (15 downto 0) ;
    resto : out bit_vector (15 downto 0)
) ;
end resto;

architecture processo of resto is
  signal dividendo_n : bit_vector (15 downto 0) := dividendo;
  signal divisor_n : bit_vector (15 downto 0) := divisor;
  begin

        process (clock, reset)
        begin
            if reset = '1' then
                fim <= '0';
                resto <= "0000000000000000";
            elsif clock'event and clock = '1' and inicio = '1'  then
              if divisor = "0000000000000000" then
                fim <= '1';
                resto <= dividendo;
              else
                while ( dividendo_n >= divisor_n) loop
                  dividendo_n <= dividendo_n - divisor_n;
                  end loop;,

                resto <= dividendo_n;
            end if;
            end if;
            end process;
end processo;   

但我不断收到此错误:在线操作符-"没有函数声明

dividendo_n <= dividendo_n - divisor_n;

有什么想法吗?我是这门语言的初学者，所以我不太了解真正发生了什么.

Any thoughts? I'm a beginner on this language so I don't know much about what is really going on.

提前致谢！

推荐答案

您只能对 VHDL 中的数字数据类型(如整数、无符号和有符号)使用数学运算.bit_vector 类型不是数字类型，因此您不能使用减法运算.

You can only use mathematical operations on numerical data types like integer, unsigned and signed in VHDL. The bit_vector type isn't a numerical type so you can't use the subtraction operation.

如果您仅限于使用 bit 或 bit_vector 类型，那么您将必须实现一个二进制减法器电路来执行此操作.

If you are limited to only using bit or bit_vector types then you will have to implement a binary subtractor circuit to perform this operation.

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