A20 产品线能否在 Haswell 和继任者身上被掩盖? [英] Can the A20 line still be masked off on Haswell and successors?

问题描述

维基百科引用了英特尔手册中的这一声明

Wikipedia quotes this statement from Intel's manual

A20M# 的功能主要由较旧的操作系统使用，现代操作系统不使用.在较新的 Intel 64 处理器上，A20M# 可能不存在.

The functionality of A20M# is used primarily by older operating systems and not used by modern operating systems. On newer Intel 64 processors, A20M# may be absent.

这是一个词，它现在实际上在手册中，但有歧义:

It is a phrase that it is actually in the manual nowadays but it is ambiguous:

1. A20M# 究竟是指引脚还是整个掩蔽物?
2. 许多指令(例如 TXT GETSEC 或 VMX 指令)的描述中都命名了 A20M 事件/中断.

1. Does A20M# actually refer to the pin only or to the whole masking thing?
2. The A20M event/interrupt is named in the description of many instructions (e.g. TXT GETSEC or VMX instructions).

我所知道的

A20M# 引脚本身已经消失，它在某个时候被 DMI 中的 VLW(虚拟传统线)接口所取代.DMI 协议足够丰富，可以提供用于断言各种传统 pin 的消息:

What I do know

The A20M# pin itself is gone, it was at some time replaced by the VLW (Virtual Legacy Wire) interface within the DMI. The DMI protocol is rich enough to have messages for asserting various legacy pin:

PCH 支持 VLW 消息作为传达状态的替代方法以下传统边带接口信号到处理器:• A20M#、INTR、SMI#、INIT#、NMI

The PCH supports VLW messages as alternative method of conveying the status of the following legacy sideband interface signals to the processor: • A20M#, INTR, SMI#, INIT#, NMI

这句话出自PCH系列8(哈斯威尔时代).

This quote comes from the PCH series 8 (Haswell era).

到目前为止，PCH 具有 A20GATE 直通功能.
当 PCH 配置为捕获对传统 8042 IO 端口(60h、64h)的访问并提供 SMI 代替(用于 USB 键盘/鼠标的 PS2 模拟)时，它可以选择让 A20 线路启用序列通过而不会被捕获.

The PCH, up to these days, has an A20GATE Pass-Through functionality.
When the PCH is configured to trap the access to the legacy 8042 IO ports (60h, 64h) and deliver an SMI instead (for PS2 simulation of USB keyboards/mice), it can optionally let the A20 line enable sequence go through without being trapped.

根据 PCH 的配置方式，这允许 EC(移动)或 SuperIO 芯片(桌面)成为命令序列的目标.

Depending on how the PCH is configured, this allows either the EC (mobiles) or the SuperIO chip (desktops) to be the target of the command sequence.

奇怪的是，PCH 系列 8(Haswell 时代)数据表报告:

Curiously enough, the PCH series 8 (Haswell era) datasheet, reports:

注意:不支持 A20M# 功能.

Note: A20M# functionality is not supported.

在 LPC 部分(EC/SuperIO 所连接的部分)，然而，这可能仅意味着 PCH 本身不模拟 A20 门和外部芯片(EC 或SuperIO) 必须处理它.

In the LPC section (where the EC/SuperIO are attached to), this, however, may only mean that the PCH itself doesn't emulate the A20 gate and an external chip (EC or SuperIO) must handle it.

在这种情况下，PCI 必须有一个引脚才能由外部芯片断言.数据表没有提到任何内容.

It that were the case, the PCI must have a pin to be asserted by the external chip. The datasheet didn't mention any.

然而，我在中文网站的某处找到了我以前的 Haswell 笔记本电脑的原理图，并且原理图显示引脚(实际上是球)AN10(又名 TP14)用作 A20M 输入引脚:

However, I've found the schematic of my previous Haswell laptop somewhere on a Chinese site and the schematic shows that the pin (actually the ball) AN10 (a.k.a. TP14) is used as the A20M input pin:

左侧的蓝光框标记为 LYNX-POINT-DH82LPMS_BGA695.

The blu box on the left is labeled as LYNX-POINT-DH82LPMS_BGA695.

GATEA20 信号的另一端来自 EC(如预期):

The other end of the GATEA20 signal comes from the EC (as expected):

IT8586E/AX 是联想的 EC(显然).

The IT8586E/AX is an EC from Lenovo (apparently).

所以 A20 线仍然可以在 Haswell 平台上被屏蔽，除非我误解了原理图.

So the A20 line could still be masked off on Haswell platforms, unless I misinterpreted the schematics.

因此，关于 A20M 方面的数据表并不完整.英特尔的 BIOS 编写器指南可能包含所有内容.

Thus, the datasheets are not complete regarding the A20M aspect. Probably the Intel's BIOS Writer Guide has it all.

A20 线可以在至少一个 Haswell 平台上禁用吗?Skylake 和继任者呢?

Can the A20 line be disabled on, at least one, Haswell platform? What about Skylake and successors?

我编写了一个简单的传统引导加载程序，用于检查 A20 线路是否已启用并尝试禁用它:

1. 如果 A20 线路被禁用，则测试结束.测试平台上存在 A20 门功能.
2. 否则，它询问 BIOS 支持的 A20 门方法，然后询问它禁用 A20 线(我信任 OSDev 的功能命名法，即启用与禁用的东西，所以我希望调用禁用 A20 行 而不是屏蔽)
3. 如果 BIOS 返回错误，程序会通过 KBC 禁用 A20 线路，使用快速 a20 方法和端口 0eeh 方法.
4. 再次测试 A20 线路状态.如果它仍然启用，手动禁用它(除非它已经完成)并再次测试.

1. If the A20 line is disabled, the test ends. The A20 gate functionality exists on the test platform.
2. Otherwise, it asks the BIOS the supported A20 gate methods and then ask it to disable the A20 line (I trusted OSDev for the nomenclature of the functions, i.e. the enable vs disable-of-what thing, so I hope that call disables the A20 line and not the masking)
3. In case the BIOS returned an error, the program disables the A20 line through the KBC, with the fast a20 method and with the port 0eeh method.
4. Test again the A20 line status. If it is still enabled, disable it manually (unless it was done already) and test it once more.

当我在 Skylake 笔记本电脑上运行此程序时，BIOS 返回仅支持快速 A20 方法并且没有发出错误信号，但 A20 线路仍处于启用状态.即使手动禁用它，A20 线仍然启用.

When I run this on my Skylake laptop, the BIOS returned that only the fast A20 method was supported and signaled no error but yet the A20 line was still enabled. Even aver manually disabling it, the A20 line was still enabled.

我得出结论，A20 线不能在 Skylake 上禁用，即它不再存在.

推荐答案

VLW 甚至在 PCH 之前就已经存在，作为 'IOAPIC virtual wire mode' 模拟来自 8259A 通过 ICH DMI/APIC 总线的 INTR 输入，而不是将 8259A INTR 指向的 LAPIC 虚拟线模式LINT 引脚 INTR 被硬连线到.PIC 模式"将 LAPIC 直接旁路到 INTR 引脚到 BSP 逻辑内核.

VLW existed even before PCH as the 'IOAPIC virtual wire mode' which emulated the INTR input from 8259A over ICH DMI / APIC bus, as opposed to the LAPIC virtual wire mode which directed the 8259A INTR to the LINT pin INTR was hardwired to. The 'PIC mode' bypassed the LAPIC directly to the INTR pin to the BSP logical core.

当第一个 PCH 到达时，Ibex Peak for Nehalem-EX，A20M# 消失了.它现在只能被 PCH 模拟为 VLW A20M 中断，而 VLW 显然是一个 未记录的 U2C(非核心到核心)IDI 操作码与 IntLog/Phy 分开.VLW 由 Ubox/IIO(以及在 LAPIC 内部)以与所有 LAPIC 共享 2 个 CPU LINT 引脚相同的方式广播到所有内核(对于 INTR、NMI 等，只有一个处理器应该有一个未屏蔽的 LINT 条目(作为 ExtInt))(这些 LINT 引脚直接连接到 INTR 渗出来自 8259A 和 NMI 源(PCH/DRAM)，而 IOAPIC 消息是通过 DMI(以前通过 APIC 总线)传输的 PCI VLW.IOH SAD 曾经包含 QPIPNCB 以进一步过滤 VLW——假设它现在存在于 IIO 中.我认为 VLW 被传递到它实际上连接到的 LINT 引脚的 LVT LINT 条目，如果 LAPIC 被禁用，则它直接进入 INTR

And when the first PCH arrived, so Ibex Peak for Nehalem-EX, A20M# disappeared. It can now only be emulated by the PCH as a VLW A20M interrupt, and VLW is apparently an undocumented U2C (uncore to core) IDI opcode separate to IntLog/Phy. VLWs are broadcast to all cores by the Ubox/IIO (and internally to the LAPICs) in the same manner that the 2 CPU LINT pins are shared by all LAPICs (for INTR, NMI etc., only one processor should have an unmasked LINT entry (as ExtInt)) (and those LINT pins are connected directly to INTR exuding from 8259A, and NMI sources (PCH / DRAM), whereas the IOAPIC messages are PCI VLWs that travel over DMI, formerly over the APIC bus). IOH SAD used to contain QPIPNCB to filter VLWs further — assumedly it now exists in the IIO. I think the VLW is passed to the LVT LINT entry of the LINT pin that INTR it is virtually connected to and if LAPIC is disabled then it goes to INTR directly

A20GATE 被 EC 驱动到 PCH 是的，这会导致 A20M VLW 或 A20M# pre-PCH(端口 92h 也可以触发 A20M#).A20M# 是 LINT 和检测A20M# 发生在宏指令边界.想必VLW也被所有核吸收，在宏指令边界中断所有逻辑核.A20M 中断 MSROM 处理程序可以像使用当前 IP 刷新和重新启动指令流一样简单，启用一个新设置，该设置更改 AGU 地址生成以屏蔽该位，从而使地址回绕.由于它是电平敏感的，当它被置低时会产生另一个中断.

A20GATE is driven to the PCH by the EC yes, and this causes the A20M VLW or A20M# pre-PCH (Port 92h also can trigger A20M#). A20M# is a separate pin to LINT and detection of A20M# happens at a macroinstruction boundary. Presumably the VLW is also absorbed by all cores, and interrupt all logical cores at the macroinstruction boundary. The A20M interrupt MSROM handler could be as simple as flushing and restarting the instruction flow with the current IP with a new setting enabled which changes the AGU address generation to mask the bit such that the address wraps round. As it's level sensitive, there will be another interrupt when it is deasserted.

关于 这个 Haswell M, A20GATE 在 LPC 界面上仍然以 GA20 的形式出现在您的Skylake U.我不确定它是否在那个原理图上连接，电线上没有 x 也没有定向网络标签，但 AG20GATE 网络标签在那里，这表明它已连接，但我不确定什么大蓝色类终端符号代表以及与没有标签的电线相比以及与带有标签符号和标签的电线相比的区别是什么.当它说不支持 A20M# 时，这意味着物理引脚，但支持生成 VLW 的 IOAPIC.支持 A20GATE 直通意味着这些设备可以启用 A20 屏蔽.

On this Haswell M, A20GATE is still here as GA20 on the LPC interface, and it's also there on your Skylake U. I'm not sure whether it is connected or not on that schematic, there's no x on the wire and there's no directional net tags but the AG20GATE net label is there, which suggests it is connected, but I'm not sure what the big blue sort-of terminal symbol represents and what the difference is compared to a labelled wire without and compared to a wire with a tag symbol as well as a label. When it says A20M# is not supported it means the physical pin, but the IOAPIC generating a VLW is supported. A20GATE passthrough is supported meaning those devices can enable A20 masking.

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