在 python 和 arduino 之间共享枚举 [英] share enum between python and arduino

问题描述

我在 python 中创建了一个 gui，它允许 arduino 控制的麦克纳姆轮车四处移动.

I have created a gui in python that allows an arduino controlled mecanum wheel cart to move around.

推车允许 8 个不同的移动方向，并且可以左右旋转.命令通过笔记本电脑(w10、python)和 arduino 之间的串行连接发送.

The cart allows for 8 different move directions and can rotate left and right. Commands are sent over a serial connection between the laptop(w10, python) and the arduino.

我在 python 中有一个 Enum 类，表示不同的移动方向.

I have an Enum class in python representing the different move directions.

我在arduino中有一个对应的枚举来解释来自python任务的命令.

I have a corresponding enum in the arduino to interprete the commands from the python task.

为两种编码环境共享一个通用枚举定义的简单方法是什么?

What is an easy way to share a single common enum definition for both coding environments?

推荐答案

没有.C/C++ 中的枚举和 python 中的 enum.Enum 是两个非常不同的东西.但是，有一个强大的解决方案.我建议从你的python代码编写C/C++/Arduino头文件.借助 python 强大的内省功能，可以轻松地使用 __dict__ 扫描你的 python 枚举/类，并编写一个你的 Arduino 代码可以使用的 .h 文件.这就是我生成与相关 python 项目中的枚举和常量匹配的 Verilog 和 SystemVerilog 标头的方式.运行 python 应用程序会生成一个新的头文件，始终保持同步.

No. Enums in C/C++ and enum.Enum in python are two very different things. However, there is a powerful solution. I suggest writing the C/C++/Arduino header from your python code. With python's powerful introspection, it's easy to scan through your python enum/class with __dict__ and write a .h file that your Arduino code can use. This is how I generate Verilog and SystemVerilog headers that match the enums and constants in related python projects. Running the python applications produces a new header file, always in sync.

一个更明确的例子

我为基于 FPGA 的微处理器构建了一个汇编程序.汇编器使用 Python，而处理器使用 Verilog 编程.所以我创建了一个像这样的 Verilog 头文件:

I've built an assembler for an FPGA-based microprocessor. The assembler is in python, while the processor is programmed in Verilog. So I create a Verilog header file like this:

# Compute the 'after' content.
content = '// opcodes.vh\n'
content += '`ifndef _opcodes_vh\n'
content += '`define _opcodes_vh\n'
content += '// DO NOT EDIT -- FILE GENERATED BY ASSEMBLER\n'
content += '// ------------------------------------\n'
content += '// OPCODES\n'
content += '// ------------------------------------\n'
A = Arch
for i in A.__dict__:
    if i.startswith('OPC_'):
        o = i.replace('OPC_', 'OPCODE_')
        s = '`define ' + o
        while len(s) < 40:
            s = s + ' '
        hexval = str(hex(A.__dict__[i])).replace('0x', '')
        decval = str(A.__dict__[i])
        s = s + "7'h" + hexval + '\t\t// ' + str(decval) + '\n'
        content += s
content += '// END OF GENERATED FILE.\n'
content += '`endif'

# Write to very specific location for Vivado to see it.
file = open(self.opcodes_filename, 'w', encoding='utf-8')
file.write(content)
file.close()

最终输出如下:

// opcodes.vh
`ifndef _opcodes_vh
`define _opcodes_vh
// DO NOT EDIT -- FILE GENERATED BY ASSEMBLER
// ------------------------------------
// OPCODES
// ------------------------------------
`define OPCODE_LD_GPR_EXPR              7'h0        // 0
`define OPCODE_LD_GPR_GPTR              7'h1        // 1
`define OPCODE_SV_EXPR_GPR              7'h2        // 2
...
`define OPCODE_IO_T                     7'h4a       // 74
`define OPCODE_TX_T                     7'h4b       // 75
// END OF GENERATED FILE.
`endif

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