ARM 中屏障(DSB、DMB、ISB)的实际用例 [英] Real-life use cases of barriers (DSB, DMB, ISB) in ARM

问题描述

我了解 DSB、DMB 和 ISB 是防止指令重新排序的障碍.我也可以为每一个找到很多很好的解释，但很难想象我必须使用它们的情况.

I understand that DSB, DMB, and ISB are barriers for prevent reordering of instructions. I also can find lots of very good explanations for each of them, but it is pretty hard to imagine the case that I have to use them.

另外，从开源代码中，我不时看到那些障碍，但很难理解为什么要使用它们.举个例子，在Linux kernel 3.7 tcp_rcv_synsent_state_process函数中，有一行如下:

Also, from the open source codes, I see those barriers from time to time, but it is quite hard to understand why they are used. Just for an example, in Linux kernel 3.7 tcp_rcv_synsent_state_process function, there is a line as follows:

    if (unlikely(po->origdev))
            sll->sll_ifindex = orig_dev->ifindex;
    else
            sll->sll_ifindex = dev->ifindex;

    smp_mb();

    if (po->tp_version <= TPACKET_V2)
            __packet_set_status(po, h.raw, status);

其中 smp_mb() 基本上是 DMB.你能给我一些你现实生活中的例子吗?这将有助于更多地了解障碍.

where smp_mb() is basically DMB. Could you give me some of your real-life examples? It would help understand more about barriers.

推荐答案

抱歉，不会像你问的那样给你一个直接的例子，因为当你已经在查看 Linux 源代码时，你有很多那些四处走动的人，他们似乎没有帮助.没有什么可耻的 - 每个理智的人至少最初都会被内存访问顺序问题弄糊涂:)

Sorry, not going to give you a straight-out example like you're asking, because as you are already looking through the Linux source code, you have plenty of those to go around, and they don't appear to help. No shame in that - every sane person is at least initially confused by memory access ordering issues :)

如果您主要是应用程序开发人员，那么您完全不必担心太多 - 无论您使用什么并发框架，都会为您解决问题.

If you are mainly an application developer, then there is every chance you won't need to worry too much about it - whatever concurrency frameworks you use will resolve it for you.

如果您主要是设备驱动程序开发人员，那么查找示例相当简单——只要您的代码依赖于先前的访问(清除中断源，写入 DMA 描述符)，然后再执行其他操作执行访问(重新启用中断，启动 DMA 事务).

If you are mainly a device driver developer, then examples are fairly straightforward to find - whenever there is a dependency in your code on a previous access having had an effect (cleared an interrupt source, written a DMA descriptor) before some other access is performed (re-enabling interrupts, initiating the DMA transaction).

如果您正在开发并发框架(或调试一个)，您可能需要更多地阅读该主题 - 但您的问题表明了表面上的好奇心而不是迫切需要?如果您正在开发自己的在线程之间传递数据的方法，而不是基于并发框架提供的原语，那么就所有意图和目的而言，这是一个并发框架.

If you are in the process of developing a concurrency framework (, or debugging one), you probably need to read up on the topic a bit more - but your question suggests a superficial curiosity rather than an immediate need? If you are developing your own method for passing data between threads, not based on primitives provided by a concurrency framework, that is for all intents and purposes a concurrency framework.

Paul McKenney 写了一篇关于内存屏障需求的优秀论文，以及它们对处理器的实际影响:内存障碍:软件黑客的硬件视图

Paul McKenney wrote an excellent paper on the need for memory barriers, and what effects they actually have in the processor: Memory Barriers: a Hardware View for Software Hackers

如果这有点过于硬核，我写了一个由 3 部分组成的博客系列，它更轻巧一些，并以特定于 ARM 的视图结束.第一部分是内存访问排序 - 介绍.

If that's a bit too hardcore, I wrote a 3-part blog series that's a bit more lightweight, and finishes off with an ARM-specific view. First part is Memory access ordering - an introduction.

但是如果它是您所追求的特定示例列表，尤其是对于 ARM 架构，那么您可能会做得比 屏障石蕊测试和食谱.

But if it is specifically lists of examples you are after, especially for the ARM architecture, you could do a lot worse than Barrier Litmus Tests and Cookbook.

超轻程序员的观点，而不是完全正确的架构版本是:

The extra-extra light programmer's view and not entirely architecturally correct version is:

• DMB - 每当一个内存访问需要对另一个内存访问进行排序时.
• DSB - 每当需要在程序执行进行之前完成内存访问时.
• ISB - 每当指令提取需要在程序中的某个点之后显式发生时，例如在内存映射更新之后或在编写要执行的代码之后.(实际上，这意味着此时丢弃任何预取指令".)

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