为什么 ARM 区分 SDIV 和 UDIV，而不区分 ADD、SUB 和 MUL? [英] Why does ARM distinguish between SDIV and UDIV but not with ADD, SUB and MUL?

问题描述

如标题所述，为什么 ARM 指令集仅在除法时区分有符号和无符号?

As stated in the title, why does the ARM instruction set distinguish between signed and unsigned only on division?

SDIV 和 UDIV 可用，但 ADD、SUB 和 MUL 不是这种情况.

SDIV and UDIV are available but that's not the case with ADD, SUB and MUL.

推荐答案

相同大小的有符号数和无符号数的加法和减法在二进制补码数学(ARM 使用)中产生完全相同的位模式，因此不需要用于单独的说明.例如，如果我们采用字节大小的值:

addition and subtraction of signed and unsigned numbers of the same size produce exactly the same bit patterns in two's complement math (which ARM uses), so there is no neeed for separate instructions. for example if we take byte-sized values:

0xFC +4 
signed: -4+4 = 0
unsigned: 252 +4 = 256 = 0x100 = 0x00 (truncated to byte)

乘法结果确实会根据操作数被解释为有符号还是无符号而改变，但是 MUL 指令产生结果的低 32 位，它们是在这两种情况下相同.在最近的 ARM 处理器中有产生完整 64 位结果的指令，这些指令成对出现，就像 SDIV 和 UDIV:UMULL、UMLAL、SSMULL、SMLAL:

Multiplication result does change depending on whether the operands are interpreted as signed or unsigned, however the MUL instruction produces only the low 32 bits of the result, which are the same in both cases. In recent ARM processors there are instructions which produce the full 64-bit result, and those come in pairs just like SDIV and UDIV: UMULL, UMLAL, SSMULL, SMLAL:

有符号和无符号长乘法，带有可选的累加，带有32 位操作数，64 位结果和累加器.

Signed and Unsigned Long Multiply, with optional Accumulate, with 32-bit operands, and 64-bit result and accumulator.

这篇关于为什么 ARM 区分 SDIV 和 UDIV，而不区分 ADD、SUB 和 MUL?的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！