更改 TTB_BASE 的更好方法是什么? [英] the better way to change TTB_BASE?

问题描述

据我所知，关闭/打开 mmu 并不是在 ARM 中切换 TTB_BASE 的好方法.那么更好的方法是什么?主要步骤是这样的吗?(ARM 920T ARMV4T)

turning off/on mmu is not a good way to switch TTB_BASE in ARM as far as I know .So what is the better way ? Is the main steps like this ? (ARM 920T ARMV4T)

1.同步 dcache --> 外部存储器
2 .clean_icache() &&invalidate_dcache() ;//这是我的问题，如果当前指令已经在 icache 中，那么我清理 &使它们无效，ARM 内核如何知道下一步是什么?ARM 内核可以再次从外部存储器中取指令吗?
3. 使整个 tlb
无效4.更改ttb基址寄存器

1 . sync dcache --> external memory
2 . clean_icache () && invalidate_dcache () ; // this is my question ,if the current instruction alreay in icache ,then I clean & invalidate them ,how can ARM core knows what is the next step ? May ARM core fetch instructions from external memory again ?
3. invalidate whole tlb
4. change the ttb base register

还有更好的方法吗?任何帮助表示赞赏！^_^

Is there another better way ? Any help appreciated ! ^_^

推荐答案

切换 TTB_BASE 与打开 MMU 非常相似.操作前有一个内存空间，操作后有另一个.您需要当前执行的代码在操作期间保持有效.选择是，

Switching the TTB_BASE is much the same as turning on the MMU. Before the operation, there is one memory space and after there is another. You need your currently executing code to remain valid during the operation. Choices are,

1. 将当前代码映射到两者的相同位置.
2. 依靠缓存进行转换.

1^st 基本上是在启用 MMU 时使用 phys == virt.在更新 TTB_BASE 时，旧版本的完整副本是最基本的.如果中断被锁定，您可能只需要映射切换代码所需的页面.这可能是一个两阶段操作，其中当前代码页最终被重新定位到某个其他内存地址.首先别名页面，分支到别名位置并删除原始页面.在每一步，刷新 TLB 和缓存都是安全的.您可能不需要这样做，具体取决于更改的上下文.但是，在第一次 flush 之后，对于 d-cache、i-cache 和 TLB 中的每一个来说，后续的刷新都不昂贵.

The 1^st is basically with phys == virt when enabling the MMU. When updating the TTB_BASE a complete copy of the old version is the most basic. If interrupts are locked, you may only need to map pages needed by the switching code. This maybe a two phase operation where the current code page is eventually re-located to some other memory address. First alias the page, branch to the alias location and remove the original page. At every step, it is safe to flush the TLB and caches. You may not need to do this, depending on the context of the change. However, after the first flush, sub-sequent flushes are not expensive for each of d-cache, i-cache and TLB.

2^nd 方法相当古怪.在StrongARM上，当启用MMU时，这被称为死亡之舞.基本上，指令是定时的，以便预取和 NOP 填充会对指令进行排序，以便 branch 从 phys 地址到 em>virt 地址就在转换时.为了更新TTB_BASE，你可以假设当前的代码页在TLB中，如果代码对齐正确，它会启动一个I-CACHE 线.在 TTB_BASE 更新之后，CPU 获取任何内存之前，可能会执行大约 6 条指令.这是一个完整的页面，如果你不刷新 TLB.

The 2^nd method is rather flakey. On the StrongARM, this was known as the dance of death, when enabling the MMU. Basically, the instructions where timed so that prefetching and NOP padding would sequence the instructions so that a branch was performed from the phys address to the virt address right at the time of transition. For updating the TTB_BASE, you can assume that the current code page is in the TLB and if the code is aligned properly it starts an I-CACHE line. There are about six instructions that maybe performed after the TTB_BASE update before any memory will be fetched by the CPU. It is a full page, if you don't flush the TLB.

我只能看到 2^nd 方法在想要频繁切换整个内存映射的 hypervisor 的情况下使用；通常管理程序只会在上下文切换上更改内存映射的一部分.2^nd 方法稍微快一些，但缺点应该很明显.

I can only see the 2^nd method being used in the case of a hypervisor that wants to switch an entire memory map frequently; generally hypervisors will only change part of the memory map on a context switch. The 2^nd method is slightly faster, but the down sides should be obvious.

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