启用性能监控注册到用户访问模式? [英] enabling performance monitoring register to user access mode?

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问题描述

我编写了代码,通过将位设置为 1 来启用用户可访问的性能监控寄存器.我在 MCR 指令中获得 ARM_BAD_INSTRUCTION,并且 MRC 运行正常.

我使用的是 armv7(cortex a5)

.cfi_startproc

MRC p15, 0, r0, c9, c14, 0 @ 读取 PMUSERENR 寄存器ORR r0, r0, #0x01 @ 设置 EN 位(位 0)MCR p15, 0, r0, c9, c14, 0 @ 写 PMUSERENR 寄存器ISB @ 同步上下文

BX lr.cfi_endproc

解决方案

根据文档,PMUSERENR 只能从特权模式写入,因此尝试从非特权用户空间写入它确实会引发未定义指令异常.

如果您想启用用户空间访问,您需要从内核(或者在内核不知道 PMU 本身的情况下可能从虚拟机管理程序/固件)执行此操作.

如果您无法控制任何此类特权软件,那么您就无法直接访问,因为这正是特权概念的重点.但是,您可能拥有的是操作系统提供的一些用户空间 API - 例如 perf events 在 Linux 上 - 让您分析和测量东西,而无需直接管理硬件;坦率地说,即使您可以启用直接访问,这通常也是更好的选择,因为用户空间仍然无法在多任务系统上正确处理所有必要的事件过滤、调度、溢出中断等.>

I have written code to enable performance monitoring register as user accessible by setting bit as 1. I getting ARM_BAD_INSTRUCTION at MCR instruction and MRC is going fine.

I am using armv7(cortex a5)

.cfi_startproc

MRC     p15, 0, r0, c9, c14, 0  @ Read PMUSERENR Register
ORR     r0, r0, #0x01           @ Set EN bit (bit 0)
MCR     p15, 0, r0, c9, c14, 0  @ Write PMUSERENR Register
ISB                             @ Synchronize context

BX lr .cfi_endproc

解决方案

As per the documentation, PMUSERENR is only writeable from privileged modes, thus an attempt to write to it from unprivileged userspace will indeed raise an undefined instruction exception.

If you want to enable userspace access, you need to do it from the kernel (or possibly from a hypervisor/firmware in the case of a kernel which doesn't know about PMUs itself).

If you don't have control of any such privileged software, well then you're not getting yourself direct access, because that's rather the point of the notion of privilege. What you might have, however, is some userspace API provided by the OS - such as perf events on Linux - to let you profile and measure stuff without the hassle of managing the hardware directly; frankly that's usually the better option even if you could enable direct access, because userspace still has no way to properly handle all the necessary event filtering, scheduling, overflow interrupts, etc. on a multitasking system.

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