可以从 EL0 刷新 arm64 缓存吗? [英] Can arm64 cache be flushed from EL0?

问题描述

我正在阅读一篇学术论文，其中指出ARM 架构还包括驱逐缓存行的指令.但是，这些指令只能在处理器处于提升特权模式时使用."

I'm reading an academic paper which states "The ARM architecture also includes instructions to evict cache lines. However, these instructions can only be used when the processor is in an elevated privilege mode."

这是真的吗?我一直在搜索 ARM 文档，但在ARM Cortex-A 系列程序员指南 for ARMv8-A"第 11.5 章 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html

Is that true? I've been searching the ARM documentation, and I don't see anything that suggests I can't do this from EL0 under "ARM Cortex-A Series Programmer’s Guide for ARMv8-A" chapter 11.5 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/BABJDBHI.html

推荐答案

这是可配置的.

来自 ARMv8 架构参考手册，第 D3-1988 页:

From the ARMv8 Architecture Reference Manual, page D3-1988:

EL0 缓存维护说明的可访问性

SCTLR_EL1.UCI 位为 DC CVAU、DC CVAC、DC CVAP 启用 EL0 访问，DC CIVAC 和 IC IVAU 指令.当 EL0 由于 SCTLR_EL1.UCI == 0 禁止使用这些指令时，在 EL0 执行这些指令之一会生成一个到 EL1 的陷阱，使用 EC = 0x18 报告.

The SCTLR_EL1.UCI bit enables EL0 access for the DC CVAU, DC CVAC, DC CVAP, DC CIVAC, and IC IVAU instructions. When EL0 use of these instructions is disabled because SCTLR_EL1.UCI == 0, executing one of these instructions at EL0 generates a trap to EL1, that is reported using EC = 0x18.

对于这些说明，需要读取访问权限.当SCTLR_EL1.UCI的值为1时:

For these instructions read access permission is required. When the value of SCTLR_EL1.UCI is 1:

• 对于DC CVAU、DC CVAC、DC CVAP和DC CIVAC指令，如果指令在 EL0 处执行，并且无法在 EL0 处读取参数中指定的地址，从而产生 Permission 错误.
• 对于IC IVAU指令，如果指令是在EL0执行，而在EL0无法读取参数中指定的地址，则IMPLEMENTATION DEFINED是否是一个权限产生故障.

• For the DC CVAU, DC CVAC, DC CVAP, and DC CIVAC instructions, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, a Permission fault is generated.
• For the IC IVAU instruction, if the instruction is executed at EL0 and the address specified in the argument cannot be read at EL0, it is IMPLEMENTATION DEFINED whether a Permission fault is generated.

软件可以读取CTR_EL0 来发现缓存维护指令所需的步幅.SCTLR_EL1.UCT 位允许 EL0 访问 CTR_EL0.当 EL0 对缓存类型寄存器的访问被禁用时，在 EL0 执行的寄存器访问指令将使用 EC = 0x18 捕获到 EL1.

Software can read the CTR_EL0 to discover the stride needed for cache maintenance instructions. The SCTLR_EL1.UCT bit enables EL0 access to the CTR_EL0. When EL0 access to the Cache Type register is disabled, a register access instruction executed at EL0 is trapped to EL1 using EC = 0x18.

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