为什么这个任务是模棱两可的? [英] Why is this assignment ambiguous?

问题描述

请注意，这个问题不是关于如何更改下面的代码以使其工作；相反，我正在寻找有关为什么编译器会发现此分配不明确的一些见解:

Please note that this question is not about how to change the code below to make it work; rather, I am looking for some insight on why a compiler would find this assignment ambiguous:

entity assignment_to_aggregates is
end;

architecture example of assignment_to_aggregates is
    type vowel_type is (a, e, i, o, u);
    type consonant_type is (b, c, d, f, g);
    type vowel_consonant_pair is record
        vowel: vowel_type;
        consonant: consonant_type;
    end record;

    signal my_vowel: vowel_type;
    signal my_consonant: consonant_type;
begin
    (my_vowel, my_consonant) <= (a, b); -- Doesn't work: "Ambiguous types in signal assignment statement."
end;

我已经使用 Modelsim Altera 10.1b 和 GHDL 0.29.1 对其进行了测试，我看到以下错误消息:

I have tested it with Modelsim Altera 10.1b and GHDL 0.29.1 and I'm seeing the following error messages:

VCOM: (vcom-1349) Ambiguous types in signal assignment statement
    Possible target types are:
        vowel_consonant_pair
        ieee.std_logic_1164.STD_ULOGIC_VECTOR
        std.STANDARD.TIME_VECTOR
        std.STANDARD.REAL_VECTOR
        std.STANDARD.INTEGER_VECTOR
        std.STANDARD.BIT_VECTOR
        std.STANDARD.BOOLEAN_VECTOR
        std.STANDARD.STRING

GHDL: type of waveform is unknown, use type qualifier

当然，如果我明确声明一个新类型(示例代码中的vowel_consonant_pair)并使用类型限定，它工作正常:

Of course, if I declare a new type explicitly (vowel_consonant_pair in the sample code) and use type qualification, it works fine:

(my_vowel, my_consonant) <= vowel_consonant_pair'(a, b); -- Works fine

但是，如果绝对没有其他类型可以匹配赋值右侧的聚合，那么为什么要这样做呢?这是一个工具问题，还是一个 VHDL 语义问题?如果是后者，有人可以提供 LRM 参考吗?

But why should this be necessary, if there is absolutely no other type that could match the aggregate on the right-hand side of the assignment? Is this a tool problem, or is this a VHDL semantics problem? If the latter, could someone please provide a LRM reference?

推荐答案

引自我对上一个问题的回答:

Quoted from my answer to the previous question:

IEEE Std 1076-1993，8.4 信号分配声明(见 -2008，10.5/10.5.2.1):

IEEE Std 1076-1993, 8.4 Signal assignment statement (see -2008, 10.5/10.5.2.1):

如果信号赋值语句的目标是一个聚合，则聚合的类型必须可从上下文，不包括聚合本身，但包括事实聚合的类型必须是复合类型.

If the target of the signal assignment statement is in the form of an aggregate, then the type of the aggregate must be determinable from the context, excluding the aggregate itself but including the fact that the type of the aggregate must be a composite type.

再补充一点:

-1993, 0.2 本文档的结构和术语(见 -2008, 1.3/1.3.1:

-1993, 0.2 Structure and terminology of this document (see -2008, 1.3/1.3.1:

此外，必须"一词用于表示强制性重量.这个词比更常见的应该"更受欢迎，因为必须"表示对本标准的不同读者有不同的含义.

Additionally, the word "must" is used to indicate mandatory weight. This word is preferred over the more common "shall," as "must" denotes a different meaning to different readers of this standard.

这是一个语义限制，必须"带有强制权重，必须满足的条件否则将在 VHDL 中生成和错误.没有限定，聚合的类型是未知的.请注意，在 2008 版标准中，that"必须被shall"取代.

It's a semantic restriction, 'must' carries a mandatory weight, a condition that must be met will otherwise generate and error in VHDL. The type of the aggregate isn't known without qualification. Note 'that' must has been supplanted by 'shall' in the 2008 version of the standard.

这里所讨论的类型是目标(左侧).IEEE Std 1076-2008 并发信号分配部分的第一句对并发信号分配语句的顺序信号分配部分中的要求进行了约束:

The type in question here is of the target (the left hand side). We're bound by to the requirement in the section on sequential signal assignment for the concurrent signal assignment statement by the first sentence of the section on concurrent signal assignment, IEEE Std 1076-2008:

11.6 并发信号赋值语句

11.6 Concurrent signal assignment statements

并发信号赋值语句表示等效的为信号赋值的过程语句.

A concurrent signal assignment statement represents an equivalent process statement that assigns values to signals.

(也在 -1993，9.5 中发现).

(Also found in -1993, 9.5).

类型通常作为名称的属性携带，但聚合不是命名对象.可以从右侧获取类型，但它也是一个聚合:

Type is generally carried as an attribute on a name, but the aggregate isn't a named object. It's possible to get the type from the right hand side except it's an aggregate too:

(my_vowel, my_consonant) <= (a, b);

Nick Gasson 的 VHDL 分析器/模拟器 nvc 更优雅地指出了解决问题的位置:

Nick Gasson's VHDL analyzer/simulator nvc points a little more elegantly to where to fix the problem:

nvc -a assignment_to_aggregate.vhdl  
** Error: no composite type in context
      File assignment_to_aggregate.vhdl, Line 11  
        (my_vowel, my_consonant) <= (a,b);  
                                    ^^^^^

(在修复因使用之前的 stackoverflow VHDL 问题发现的缺失语义检查而导致的详细说明崩溃"之后).

(Following a fix for an elaboration 'crash' caused by a missing semantic check found using a previous stackoverflow VHDL question).

你怎么能在右手边打字?

How can you type the right hand side?

来自 IEEE 标准 1076-1993:

From IEEE Std 1076-1993:

7.3.4 限定表达式

7.3.4 Qualified expressions

限定表达式是一个基本操作(见介绍第 3 节)用于明确说明类型，可能还有子类型，作为表达式或聚合的操作数.

A qualified expression is a basic operation (see the introduction to Section 3)that is used to explicitly state the type, and possibly the subtype, of an operand that is an expression or an aggregate.

 qualified_expression ::=
        type_mark ' ( expression )
      | type_mark ' aggregate

操作数必须与类型标记的基类型具有相同的类型.限定表达式的值是操作数的值.这合格表达式的计算会计算操作数并检查它的值属于类型标记所表示的子类型.

The operand must have the same type as the base type of the type mark. The value of a qualified expression is the value of the operand. The evaluation of a qualified expression evaluates the operand and checks that its value belongs to the subtype denoted by the type mark.

注意--只要枚举文字或聚合的类型不是从上下文中知道，可以使用限定的表达式来说明明确的类型.

NOTE--Whenever the type of an enumeration literal or aggregate is not known from the context, a qualified expression can be used to state the type explicitly.

在任何 VHDL 标准版本中都没有上下文"的词汇表定义.一个有效的定义可能包含这样一个概念，即某物的声明是可见的，而没有限定的聚合类型则不是这种情况.

There isn't a glossary definition of 'context' in any of the VHDL standard versions. A working definition might include the notion that the declaration for something is visible, which isn't the case for the type of an aggregate without qualification.

我写了答案 到上一个问题，我专门介绍了记录类型声明，以解决无法在限定表达式中使用类型标记修饰聚合的问题.请注意，没有声明为元音辅音对记录的子类型(信号和).需要类型声明，而不是实际记录.

I wrote the answer to the previous question and I introduced the record type declaration specifically to address the lack of ability to decorate the aggregate with a type mark in a qualified expression. Note that there is no subtype (signal and) declared as a vowel_consonant_pair record. The type declaration was needed, not an actual record.

另请注意，我在 ghdl-0.31 上提交了一个错误，该错误已修复源代码树，但此后一直没有实际发布 - ghdl barfs 当它无法辨别聚合的类型时.如果您不限定表达式，则较新版本的 ghdl 不会崩溃.

Also note I submitted a bug on ghdl-0.31 which has been fixed source tree but there hasn't been an actual release since - ghdl barfs when it can't discern the type of an aggregate. A newer version of ghdl won't crash if you don't qualify the expression.

有关 stackoverflow 的问题通常对改进开源 VHDL 工具做出了巨大贡献.

Questions on stackoverflow generally make a wonderful contribution to improving open source VHDL tools.

我将标准放在手边，通常能够引用章节和诗句.这可能需要做很多工作，尽管没有置换索引，但通过彻底阅读标准，您几乎无法找到有关 VHDL 的信息，而且您必须灌输术语以了解您所了解内容的重要性阅读.

I keep the standards handy and usually am able to cite chapter and verse. It can be a lot of work, there's very little you can't find out about VHDL by a thorough reading of the standard although there isn't a permuted index and you have to be inculcated in the terminology to understand the significance of what you read.

就像您当前问题的答案一样，标准中的参考可以引出标准的另一部分.

Like the answer to your current question a reference in the standard can lead to another part of the standard.

Jim Lewis 引用的 comp.lang.vhdl FAQ在最近的一个答案中是一个很好的参考，但有时缺乏权威性的强调，谨慎使用 -1993 标准的参考.

The comp.lang.vhdl FAQ quoted by Jim Lewis in a recent answer is a wonderful reference but sometimes lacks authoritative emphasis, using references to the -1993 standard sparingly.

参见常见问题解答，4.2.18 如何解决类型歧义表达式.

您的困惑似乎源于 Modelsim 错误消息，建议解决歧义所需的可能"类型.注意4.2.18中的第一句:

Your confusion seems to stem from the Modelsim error messages suggesting 'possible' types needed to resolve ambiguity. Note the first sentence in the 4.2.18:

VHDL 是一种强类型语言.因此，编译器不执行任何隐式类型转换或尝试猜测"类型一个表达式.

VHDL is a strongly typed language. Hence, the compiler does not perform any implicit type conversions or attempt to "guess" the type of an expression.

聚合是一个表达式(参见 7.3.2/9.3.3 聚合，-1993/-2008).

And an aggregate is an expression (See 7.3.2/9.3.3 Aggregates, -1993/-2008).

vcom 错误消息提供的大多数可能的类型声明对于由两个不同类型元素组成的聚合来说是不准确的——a 是元音类型值的枚举名称，而 b 是辅音类型值的枚举.

Most of the possible type declarations provided by the vcom errror message are not accurate for the aggregate which is comprised of two disparate type elements - a is an enumeration name for a value of vowel_type and b is an enumeration for a value of consonant_type.

随 vcom 错误提供的类型似乎是所有通过局部声明 (vowel_consonant_pair) 或上下文子句(std_ulogic_vector、real_vector、integer_vector、bit_vector、boolean_vector、string，在 ieee.std_logic_1164 或 std 中共同找到)可见的复合类型.标准).

The types provided with the vcom error appear to be all the composite types made visible by local declaration (vowel_consonant_pair) or context clause (std_ulogic_vector, real_vector, integer_vector, bit_vector, boolean_vector, string, collectively found in ieee.std_logic_1164 or std.standard).

那一堆中只有一个是有效的(vowel_consonant_pair).请注意，VHDL 分析器没有猜测，而是根据语义规则(信号分配语句 8.4/10.5.2.1，...聚合的类型必须可以从上下文中确定，不包括聚合本身，但包括聚合的类型必须是复合类型这一事实").该规则给出了可能的候选列表、可用的复合类型，同时不允许猜测(排除聚合本身").

Of that bunch only one would be valid (vowel_consonant_pair). Notice the VHDL analyzer didn't guess, instead requiring the correct type to be made available from context as an object decoration (type qualification) as a result of a semantic rule (Signal assignment statement 8.4/10.5.2.1, "...the type of the aggregate must be determinable from the context, excluding the aggregate itself but including the fact that the type of the aggregate must be a composite type"). The rule giving the list of possible candidates, available composite types while disallowing guessing ("excluding the aggregate itself").

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