为什么选择“ARM 体系结构的过程调用标准"?(AAPCS) 要求 SP 是 8 字节对齐的? [英] Why "Procedure Call Standard for the ARM Architecture" (AAPCS) requires SP to be 8-byte aligned?

问题描述

由于这是一个反复出现的话题，我提出了一个关于它的问题.

根据AAPCS:p><块引用><块引用>

5.2.1.1 通用堆栈约束

• SP mod 4 = 0.堆栈必须始终与字边界对齐

5.2.1.2 公共接口的堆栈约束

• SP mod 8 = 0.堆栈必须是双字对齐的.

8 字节对齐背后的原因是什么?

解决方案

可能的原因有很多；

1. 需要它的工具.
2. ldrd/strd 在某些架构上需要它.
3. 许多 ARM 总线都是 64 位宽的.8 字节对齐将导致更快的内存访问.
4. 缓存也是对齐的，并且通常大于 64 位(128B、1024b).
5. 页表和 TLB 将跨越大于 64 位(1k 或 4k+)的大小.
6. 标记指针可用于异常(C++、信号等)帧遍历代码中.八字节对齐允许使用额外的位.

唯一重要的是，标准是这么说的.如果您不遵守此规定，您的编译器和工具将无法互操作.主要是第 1 项将意味着这些工具将无法互操作.代码将获取错误的值，否则将引发机器异常.如果异常处理代码使用了第 5 项，它也可能会破坏.

主要是，有人做出选择这一事实意味着人们可以利用这一事实来实现他们喜欢的任何用途，并且仍然可以互操作.编译器将遵循标准的建议，因为它们需要与可能不是由它们生成的其他库和代码进行互操作.

同样重要的是要注意这适用于 ARMv7/A.例如，Cortex M3 (CM3_r0) 的修订版 0 在进入异常时不会将 SP 与 8 的倍数对齐.

ABI for ARM® 架构咨询说明 – SP必须是 8 - 进入 AAPCS - 符合函数时的字节对齐

Since this is a recurring topic, I'm putting up a question about it.

According to AAPCS:

5.2.1.1 Universal stack constraints

• SP mod 4 = 0. The stack must at all times be aligned to a word boundary

5.2.1.2 Stack constraints at a public interface

• SP mod 8 = 0. The stack must be double-word aligned.

What is the rational behind 8-byte alignment?

解决方案

There are many possible reasons;

1. Tools from require it.
2. ldrd/strd require it on certain architectures.
3. Many ARM buses are 64bit wide. 8byte alignment will result in faster memory access.
4. Caches are also aligned and generally wider than 64 bits (128B, 1024b).
5. Page table and TLBs will straddle sizes larger than 64bits (1k or 4k+).
6. Tagged pointers can be used in exception (C++, signals, etc) frame walking code. The eight byte alignment allows for an additional bit to be used.

The only one that matters, The standard says so. Your compiler and tools will not inter-operate if you do not comply with this. Mainly item 1 will mean that the tools will not inter-operate. The code will fetch the wrong values or a machine exception will be thrown. If exception handling code makes use of item 5, it may also break things.

Mainly, that fact that someone made the choice means that people can take advantage of this fact for what ever use they like and still inter-operate. Compilers will follow the advice of the standard because they need to inter-operate with other libraries and code which may not have been generated by them.

It is also important to note that this applies to ARMv7/A. For example revision 0 of Cortex M3 (CM3_r0) does not align SP to a multiple of 8 on entry to exceptions.

ABI for the ARM® Architecture Advisory Note – SP must be 8 - byte aligned on entry to AAPCS - conforming functions

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