条件组件声明和以下 if 等式 [英] conditional component declaration and a following if equation

问题描述

我正在尝试构建一个模型，该模型将根据是否存在某些组件(在我的情况下为流体端口)具有略微不同的方程.

I am trying to build a model that will have slightly different equations based on whether or not certain components exist (in my case, fluid ports).

下面的代码不起作用:

parameter Boolean use_component=false;
Component component if use_component;
equation
if use_component then
  component.x = 0;
end if;

我该如何解决这个问题?

How can I work around this?

推荐答案

如果要使用条件组件，需要注意一些限制.Modelica 3.3 规范的第 4.4.5 节很好地总结了它.它说如果条件为假，则组件、其修饰符和任何连接方程涉及组件，被删除".我将在几秒钟内向您展示如何使用它来解决您的问题，但首先我想解释一下为什么您的解决方案不起作用.

If you want to use condition components, there are some restrictions you need to be aware of. Section 4.4.5 of the Modelica 3.3 specification sums it up nicely. It says "If the condition is false, the component, its modifiers, and any connect equations involving the component, are removed". I'll show you how to use this to solve your problem in just a second, but first I want to explain why your solution doesn't work.

问题与检查模型有关.在您的情况下，很明显方程 component.x 和组件 component 要么都存在，要么都不存在.那是因为您已将它们绑定到同一个布尔变量.但是如果你没有这个怎么办:

The issue has to do with checking the model. In your case, it is obvious that the equation component.x and the component component either both exist or neither exist. That is because you have tied them to the same Boolean variable. But what if you had don't this:

parameter Real some_number;
Component component if some_number*some_number>4.0;
equation
if some_number>=-2 and some_number<=2 then
  component.x = 0;
end if;

我们可以看到这在逻辑上与您的情况相同.当 component 不存在时，component.x 就没有机会存在.但是我们能一般地证明这些事情吗?没有.

We can see that this logically identical to your case. There is no chance for component.x to exist when component is absent. But can we prove such things in general? No.

因此，当引入条件组件时，实现了保守语义，始终可以轻松确保所涉及的变量和方程组永远不会不同步".

So, when conditional components were introduced, conservative semantics were implemented which can always trivially ensure that the sets of variables and equations involved never get "out of sync".

让我们回到规范所说的内容:如果条件为假，则组件、其修饰符以及任何连接方程涉及该组件，被删除"

Let us to return to what the specification says: "If the condition is false, the component, its modifiers, and any connect equations involving the component, are removed"

对于您的情况，解决方案可能非常简单.根据您声明x"的方式，您可以只对 component 进行修改，即

For your case, the solution could potentially be quite simple. Depending on how you declare "x", you could just add a modification to component, i.e.

parameter Boolean use_component=false;
Component component(x=0) if use_component;

这样做的好处是修改仅适用于 component，如果 component 不存在，则修改(方程式)也不存在.所以变量 x 和它的相关方程是同步的".但这并不适用于所有情况(IIRC，x 必须有一个 input 限定符才能工作......也许在你的情况下这是可能的?).

The elegance of this is that the modification only applies to component and if component isn't present, neither is the modification (equation). So the variable x and its associated equation are "in sync". But this doesn't work for all cases (IIRC, x has to have an input qualifier for this to work...maybe that is possible in your case?).

还有两种选择.首先，将方程 component.x 放入 component 中.第二个是在 component 上引入一个连接器，如果连接，它将生成您想要的方程式.与修改案例一样(这不是巧合)，您可以将 x 与某种输入连接器相关联，然后执行以下操作:

There are two remaining alternatives. First, put the equation component.x inside component. The second is to introduce a connector on component that, if connected, will generate the equation you want. As with the modification case (this is not a coincidence), you could associate x with an input connector of some kind and then do this:

parameter Boolean use_component;
Component component if use_component;
Constant zero(k=0);
equation
connect(k.y, component.x);

现在，我可以想象，在考虑了所有三种情况(修改、内化方程和使用 connect)之后，您得出的结论是它们都不起作用.如果是这种情况，那么我会谦虚地建议您对如何设计组件有疑问.出现这些限制的原因与检查组件自身的正确性的必要性有关.这要求组件是完整的(规范术语中的平衡").

Now, I could imagine that after considering all three cases (modification, internalize equation and use connect), you come to the conclusion that none of them will work. If this is the case, then I would humbly suggest that you have an issue with how you have designed the component. The reason these restrictions arise is related to the necessity to check components by themselves for correctness. This requires that the component be complete ("balanced" in the terminology of the specification).

如果您无法使用我上面提到的方法解决问题，那么我怀疑您确实存在平衡问题，并且您可能需要以某种方式重新定义组件的边界.如果是这种情况，我建议您在此处打开另一个问题，详细说明您正在尝试做什么.

If you cannot solve the problem with approaches I mentioned above, then I suspect you really have a balancing issue and that you probably need to redefine the boundaries of your component somehow. If this is the case, I would suggest you open another question here with details of what you are trying to do.

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