ISR 和函数调用的区别? [英] Difference between ISR and Function Call?

问题描述

我想了解 ISR(中断服务程序)和函数调用之间的区别.

I want to understand difference between ISR (Interrupt Service Routine) and Function call.

我觉得从硬件的角度来看，函数调用和 ISR 是一样的.如果我错了，请纠正我.我能找到的关于 ISR 和函数调用的所有信息如下:

I feel both the function call and ISR are the same from the hardware perspective. Please Correct me if I am wrong. All I could found about ISR and Function call is as follows:

ISR:

• 在执行过程中随时可能发生的异步事件程序

• Asynchronous event that can occur any time during the execution of the program

将 PC、标志和寄存器保存在堆栈中，并禁用所有中断并加载 ISR 的地址

Saves the PC, Flags and registers on the stack and disables all the interrupts and loads the address of the ISR

ISR 不能有可传递给它的参数

ISR cannot have arguments that can be passed to it

功能:

• 每当有函数调用时发生

• Occurs when ever there is a function call

将 PC 和寄存器保存在堆栈中

Saves the PC and registers on the stack

可以有参数

可以返回值

对执行的大小和持续时间没有限制

No restriction on the size and duration of execution

除此之外还有什么不同吗?请告诉我.我还阅读了有关 ISR 的函数调用是如何发生的.请在上面突出显示.

Is there any more difference other than this ? Please let me know. I have also read about having a function call from ISR how does that take place. Please highlight on it.

推荐答案

它们不一定和你在 ISR 的第一点中所说的一样:中断是异步的，因此必须以某种方式中断"主处理器的工作(s).

They are not necessarily the same as you statet in the first point on ISRs: Interrupts are asynchronous and therefore have to somehow 'interrupt' the work of the main processor(s).

例如，让我们看看这个用地址修饰的 MIPS 代码，它没有任何用处:

For example, lets look at this MIPS code decorated with addresses, which does not make anything useful:

4000.       add $1, $2, $3
4004.       sw $ra, 0($sp)
4008.       jal subr   # function call, sets $ra to 4012 and jumps to 4024
4012.       lw $ra, 0($sp)
4016.       jr $ra
4020.
4024. subr: sub $2, $1, $3
4028.       jr $ra

此代码可以从主处理器处理:算术运算(第 1、7 行)由算术单元完成，内存访问(第 2、4 行)由内存控制器完成，跳转(第 3、5 行), 8) 也由主 cpu 完成.(jal的实际地址是在绑定object文件时设置的.)

This code can be handeled from the main processor: the arithmetic operations (lines 1, 7) are done by the arithmetic unit, memory access (lines 2, 4) by the memory controller, and the jumps (lines 3, 5, 8) are done by the main cpu as well. (The actual address of jal is set during binding of the object file.)

这是用于函数调用的.在任何时候都可以确定代码现在在哪里以及在下一个时间点执行哪些代码(即当程序计数器递增时:PC+=4).

This is for function calls. At any time it is determined, where the code is right now and which code is executed at the next point in time (i.e. when the programm counter is incremented: PC+=4).

现在重点来了，当您的函数执行复杂的操作但您仍希望软件对击键做出反应时.然后一个所谓的协处理器开始发挥作用.这个协处理器一直等到某个事件(如键盘上的击键)发生，然后调用中断处理程序.这是位于内存中某个地址的代码块.

Now there comes the point, when your functions do something complicated but you still want the software to react on a key stroke. Then a so called coprocessor comes into play. This coprocessor waits until some event (like a key stroke on your keyboard) occurs, and then calls the interrupt handler. This is a block of code located on a certain address in the memory.

想一想，处理器在上面的计算中，但同时你想在地址 keys 上存储击键次数.然后你编写一个从地址 0x80000180 开始的程序(这在 MIPS 中定义为异常处理程序地址):

Think, the processor is in the computation above, but in the meantime you want to store the number of key strokes on address keys. Then you write a programm starting at address 0x80000180 (this is defined as the exeption handler address in MIPS):

lw $at, keys
addi $at, $at, 1
sw $at, keys
eret

现在按键会发生什么?

1. 协处理器知道击键
2. 保存主处理器的当前PC
3. 主处理器的PC设置为0x80000180，执行中断代码
4. 在 eret 上，PC 设置为中断发生前主处理器的 PC
5. 主程序的执行在那里继续.

1. The coprocessor gets aware of the keystroke
2. The current PC of the main procesor is saved
3. The PC of the main processor is set to 0x80000180, the interrupt code is executed
4. On eret the PC is set to the PC of the main processor before the interrupt occured
5. The execution of the main progamm continues there.

这里在第 2 步和第 3 步之间从正常执行切换到中断处理，然后从第 4 步到第 5 步.

Here there is a switch from normal execution to interrupt handling between steps 2 and 3 and back again from 4 to 5.

注意:我已经简化了很多，但应该清楚的是，中断与函数调用有何不同，以及硬件如何必须具有额外的中断处理能力.

Note: I have simplified this a lot, but it should be clear, how interrupts are different from function calls, and how the hardware has to have additionall capabilities for interrupt handling.

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