如何让我的基于x64的过程比对异常？ [英] How to enable alignment exceptions for my process on x64?
问题描述
我很好奇，看看我的64位应用程序的定位错误受到影响。
I'm curious to see if my 64-bit application suffers from alignment faults.
在Windows中，生成一个校准故障会引发异常的应用程序， EXCEPTION_DATATYPE_MISALIGNMENT 。
In Windows, an application program that generates an alignment fault will raise an exception,
EXCEPTION_DATATYPE_MISALIGNMENT.
-
在Itanium ，默认情况下，操作系统（OS）将这个异常可见的应用程序，并终止处理程序可能会在这些情况下非常有用。如果不建立一个处理程序，那么你的程序将挂起或崩溃。在清单3中，我们提供了一个示例，说明如何捕捉到EXCEPTION_DATATYPE_MISALIGNMENT例外。
On the Itanium, by default, the operating system (OS) will make this exception visible to the application, and a termination handler might be useful in these cases. If you do not set up a handler, then your program will hang or crash. In Listing 3, we provide an example that shows how to catch the EXCEPTION_DATATYPE_MISALIGNMENT exception.
x86架构，操作系统不会使定位故障可见的应用程序。关于这两个平台，也将遭受性能降低上的对准错，但它会显著比在安腾不太严重，因为硬件将使存储器的多个访问来检索未对齐数据
On the x86 architecture, the operating system does not make the alignment fault visible to the application. On these two platforms, you will also suffer performance degradation on the alignment fault, but it will be significantly less severe than on the Itanium, because the hardware will make the multiple accesses of memory to retrieve the unaligned data.
在x64体系结构，对准异常默认情况下禁用，以及修复起坐都是由硬件完成。 应用程序可以通过设置几个寄存器位的使能对齐异常的，在这种情况下，例外将提高，除非得到了用户的操作系统屏蔽例外与 SEM_NOALIGNMENTFAULTEXCEPT 。 （有关详细信息，请参阅 AMD架构程序员手册第2卷：系统编程的）
On the x64 architecture, the alignment exceptions are disabled by default, and the fix-ups are done by the hardware. The application can enable alignment exceptions by setting a couple of register bits, in which case the exceptions will be raised unless the user has the operating system mask the exceptions with SEM_NOALIGNMENTFAULTEXCEPT. (For details, see the AMD Architecture Programmer's Manual Volume 2: System Programming.)
忽略的方向咨询 AMD架构程序员手册，我反而会咨询的英特尔64和IA-32架构软件开发人员手册
Ignoring the direction to consult the AMD Architecture Programmer's Manual, i will instead consult the Intel 64 and IA-32 Architectures Software Developer’s Manual
在CPL为3，内存引用对准可以通过设置检查 AM国旗在CR0寄存器和AC标志EFLAGS寄存器中的。未对齐的内存 引用产生对齐异常（#AC）。处理器不会产生 当在特权级别0，1，或2见表6-7的操作比对异常 的对准要求说明时启用对齐检查。
5.10.5 Checking Alignment
When the CPL is 3, alignment of memory references can be checked by setting the AM flag in the CR0 register and the AC flag in the EFLAGS register. Unaligned memory references generate alignment exceptions (#AC). The processor does not generate alignment exceptions when operating at privilege level 0, 1, or 2. See Table 6-7 for a description of the alignment requirements when alignment checking is enabled.
优秀。我不知道这意味着什么，但优秀的。
Excellent. I'm not sure what that means, but excellent.
再有就是也：
控制寄存器（CR0，CR1，CR2，CR3，CR4和;参见图2-6）确定工作 处理器的模式和当前正在执行的任务的特性。 这些寄存器都是32位的所有32位模式和兼容模式。
2.5 CONTROL REGISTERS
Control registers (CR0, CR1, CR2, CR3, and CR4; see Figure 2-6) determine operating mode of the processor and the characteristics of the currently executing task. These registers are 32 bits in all 32-bit modes and compatibility mode.
在64位模式中，控制寄存器被扩展到64位。该MOV CR n的说明 用于操作的寄存器位。操作数大小prefixes这些指令 将被忽略。
In 64-bit mode, control registers are expanded to 64 bits. The MOV CRn instructions are used to manipulate the register bits. Operand-size prefixes for these instructions are ignored.
控制寄存器总结如下，每个建筑定义的控制 这些控制寄存器场均单独描述。在图2-6中的宽度 在64位模式寄存器中指示括号（除了CR0）。 - CR0 - 包含控制操作模式和状态的系统控制标志 处理器
The control registers are summarized below, and each architecturally defined control field in these control registers are described individually. In Figure 2-6, the width of the register in 64-bit mode is indicated in parenthesis (except for CR0). - CR0 — Contains system control flags that control operating mode and states of the processor
AM
对齐掩码（位18 CR0的） - 启用自动对齐检查
当设置;禁用时对齐检查清楚。对齐检查，
进行仅在AM标志被设置，AC标志在EFLAGS寄存器是
集，CPL为3，并且所述处理器被在被保护的或virtual-操作
8086模式。
AM
Alignment Mask (bit 18 of CR0) — Enables automatic alignment checking
when set; disables alignment checking when clear. Alignment checking is
performed only when the AM flag is set, the AC flag in the EFLAGS register is
set, CPL is 3, and the processor is operating in either protected or virtual-
8086 mode.
我实际使用的语言是德尔福，但pretend它的语言无关的伪code：
I tried
The language i am actually using is Delp but pretend it's language agnostic pseudocode:
void UnmaskAlignmentExceptions()
{
asm
mov rax, cr0; //copy CR0 flags into RAX
or rax, 0x20000; //set bit 18 (AM)
mov cr0, rax; //copy flags back
}
第一个指令
mov rax, cr0;
失败，特权指令异常。
fails with a Privileged Instruction exception.
如何启用对齐例外我的x64处理？
How to enable alignment exceptions for my process on x64?
我发现，在x86具有指令：
I discovered that the x86 has the instruction:
-
PUSHF，POPF：PUSH / POP /关闭堆栈前16位EFLAGS的 -
PUSHFD，POPFD：PUSH / POP /关闭栈中所有的32位EFLAGS的
PUSHF,POPF: Push/pop first 16-bits of EFLAGS on/off the stackPUSHFD,POPFD: Push/pop all 32-bits of EFLAGS on/off the stack
这随后导致我x64版本：
That then led me to the x64 version:
-
PUSHFQ，POPFQ：PUSH / POP /关闭堆栈RFLAGS四
PUSHFQ,POPFQ: Push/pop the RFLAGS quad on/off the stack
（64位世界 EFLAGS 重命名 RFLAGS ）。
(In 64-bit world the EFLAGS are renamed RFLAGS).
所以我写了：
void EnableAlignmentExceptions;
{
asm
PUSHFQ; //Push RFLAGS quadword onto the stack
POP RAX; //Pop them flags into RAX
OR RAX, $20000; //set bit 18 (AC=Alignment Check) of the flags
PUSH RAX; //Push the modified flags back onto the stack
POPFQ; //Pop the stack back into RFLAGS;
}
和它没有崩溃或触发保护异常。我不知道，如果它做什么，我希望它。
And it didn't crash or trigger a protection exception. I have no idea if it does what i want it to.
推荐答案
在x64上运行的应用程序可以访问一个标志寄存器（有时被称为的 EFLAGS ）。该寄存器位18允许应用程序获得异常时发生对准误差。因此从理论上讲，所有的程序必须做，使对齐错误异常被修改标志寄存器。
Applications running on x64 have access to a flag register (sometimes referred to as EFLAGS). Bit 18 in this register allows applications to get exceptions when alignment errors occur. So in theory, all a program has to do to enable exceptions for alignment errors is modify the flags register.
为了针对实际工作中，操作系统内核必须设置 CR0 的第18位，以允许它。而Windows操作系统不会做到这一点。为什么不呢？谁知道？
In order for that to actually work, the operating system kernel must set cr0's bit 18 to allow it. And the Windows operating system doesn't do that. Why not? Who knows?
应用程序无法在控制寄存器中设置的值。只有内核可以做到这一点。设备驱动程序在内核中运行，所以可以设置这一点。
Applications can not set values in the control register. Only the kernel can do this. Device drivers run inside the kernel, so they can set this too.
这是可能的渣土约，并得到通过创建一个设备驱动程序（见工作<一个href="http://blogs.msdn.com/b/oldnewthing/archive/2004/07/27/198410.aspx#199239">http://blogs.msdn.com/b/oldnewthing/archive/2004/07/27/198410.aspx#199239而后面的评论）。请注意，这个帖子是超过十年的历史，所以某些环节都死了。
It is possible to muck about and try to get this to work by creating a device driver (see http://blogs.msdn.com/b/oldnewthing/archive/2004/07/27/198410.aspx#199239 and the comments that follow). Note that this post is over a decade old, so some of the links are dead.
您可能还会发现这条评论（有的在这个问题其他的答案）是有用的：
You might also find this comment (and some of the other answers in this question) to be useful:
Larry Osterman - 07-28-2004 2:22 AM
我们实际上是建立一个版本的NT与排列的异常接通86（你可以做到这一点作为天翼提到）。
We actually built a version of NT with alignment exceptions turned on for x86 (you can do that as Skywing mentioned).
我们迅速转向，因为这打破了:)的应用程序的数量而过，
We quickly turned it off, because of the number of apps that broke :)
这篇关于如何让我的基于x64的过程比对异常？的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
