无法在C＃应用程序使用多个处理器组对我的线程 [英] Unable to use more than one processor group for my threads in a C# app
问题描述
根据 MSDN文档并的Stephen Toub回答，我的C＃应用程序应该使用每个处理器组的每个逻辑处理器，因为它被配置为要求（见下面我的App.config）。
According to MSDN documentation and Stephen Toub answer, my C# app should use every Logical Processor of every Processor Group because it is configured as required (see my App.config below).
我与NUMA架构上运行我的一个Windows Server 2012中的应用程序：2×[CPU至强E5-2697 v3的14芯每激活超级线程] => 2×14×2 = 56逻辑处理器
I run my app on a windows server 2012 with a NUMA architecture: 2 x [cpu Xeon E5-2697 v3 at 14 cores each with Hyper Thread activated] => 2 x 14 x 2 = 56 Logical Processors.
我的应用程序启动80线程无论是从Thread类或的Parallel.For，并在这两种情况下，只需要28逻辑处理器，都来自同一个处理器组。
My app start 80 threads either from "Thread Class" or "Parallel.For" and in both case it only takes 28 Logical Processors, all from the same Processor Group.
为什么任务调度分配上只有一个处理器组我的主题
Why does the Task scheduler assign my threads on only one Processor Group?
我的代码可在的GitHub 或可执行文件可以在我的 Home网站
My code is available at GitHub or the executable could be downloaded at my Home website
我已经问上的 social.msdn.microsoft.com < 。/ A>没有任何答案
I've already asked this question on social.msdn.microsoft.com without any answers.
-
更新2015年1月26日：我在报道的 connect.microsoft.com
Update 2015-01-26: I reported a bug at connect.microsoft.com
更新2015年1月30日：我加CoreInfo倾倒作为附加参考
更新2015-01- 30：也出现该问题的的Prime95 它
只提供选择28线程（不是C＃相关）
更新2015年1月30日：我的工具现在显示更像是每节点处理器
掩码信息。这听起来像我没有访问到其他节点
（我不运行的节点）
更新2015年2月2日，我们没有这个特殊的
服务器上安装了思杰（对不起，我错了）
更新2015年2月2日，我们联系了HP ...
更新2015年2月3日，增加了更多的信息到我的程序来显示每个线程
processorGroup和几个小玩意儿。
更新2015年2月17日，谈到惠普开发团队后，我更新了我的答案
，以反映我学到了什么。 （只是想指出，我从惠普收到了极好的支持）
更新2015年5月13日，惠普证实了问题客户咨询
笔记。看到这个链接的文档ID： c04650594
Update 2015-05-13, HP confirmed the problem in a "Customer Advisory" note. See this linked document id: c04650594
设置我的.NET 4.5（或4.5.1）App.Config中来：
I set my .Net 4.5 (or 4.5.1) App.Config to:
<?xml version="1.0" encoding="utf-8"?>
<configuration>
<runtime>
<Thread_UseAllCpuGroups enabled="true"></Thread_UseAllCpuGroups>
<GCCpuGroup enabled="true"></GCCpuGroup>
<gcServer enabled="true"></gcServer>
</runtime>
<startup>
<supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5.1"/>
</startup>
这是 CoreInfo 从微软：
Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz
Intel64 Family 6 Model 63 Stepping 2, GenuineIntel
Microcode signature: 00000023
HTT * Hyperthreading enabled
HYPERVISOR - Hypervisor is present
VMX * Supports Intel hardware-assisted virtualization
SVM - Supports AMD hardware-assisted virtualization
X64 * Supports 64-bit mode
SMX * Supports Intel trusted execution
SKINIT - Supports AMD SKINIT
NX * Supports no-execute page protection
SMEP * Supports Supervisor Mode Execution Prevention
SMAP - Supports Supervisor Mode Access Prevention
PAGE1GB * Supports 1 GB large pages
PAE * Supports > 32-bit physical addresses
PAT * Supports Page Attribute Table
PSE * Supports 4 MB pages
PSE36 * Supports > 32-bit address 4 MB pages
PGE * Supports global bit in page tables
SS * Supports bus snooping for cache operations
VME * Supports Virtual-8086 mode
RDWRFSGSBASE * Supports direct GS/FS base access
FPU * Implements i387 floating point instructions
MMX * Supports MMX instruction set
MMXEXT - Implements AMD MMX extensions
3DNOW - Supports 3DNow! instructions
3DNOWEXT - Supports 3DNow! extension instructions
SSE * Supports Streaming SIMD Extensions
SSE2 * Supports Streaming SIMD Extensions 2
SSE3 * Supports Streaming SIMD Extensions 3
SSSE3 * Supports Supplemental SIMD Extensions 3
SSE4a - Supports Streaming SIMDR Extensions 4a
SSE4.1 * Supports Streaming SIMD Extensions 4.1
SSE4.2 * Supports Streaming SIMD Extensions 4.2
AES * Supports AES extensions
AVX * Supports AVX intruction extensions
FMA * Supports FMA extensions using YMM state
MSR * Implements RDMSR/WRMSR instructions
MTRR * Supports Memory Type Range Registers
XSAVE * Supports XSAVE/XRSTOR instructions
OSXSAVE * Supports XSETBV/XGETBV instructions
RDRAND * Supports RDRAND instruction
RDSEED - Supports RDSEED instruction
CMOV * Supports CMOVcc instruction
CLFSH * Supports CLFLUSH instruction
CX8 * Supports compare and exchange 8-byte instructions
CX16 * Supports CMPXCHG16B instruction
BMI1 * Supports bit manipulation extensions 1
BMI2 * Supports bit manipulation extensions 2
ADX - Supports ADCX/ADOX instructions
DCA * Supports prefetch from memory-mapped device
F16C * Supports half-precision instruction
FXSR * Supports FXSAVE/FXSTOR instructions
FFXSR - Supports optimized FXSAVE/FSRSTOR instruction
MONITOR * Supports MONITOR and MWAIT instructions
MOVBE * Supports MOVBE instruction
ERMSB * Supports Enhanced REP MOVSB/STOSB
PCLMULDQ * Supports PCLMULDQ instruction
POPCNT * Supports POPCNT instruction
LZCNT * Supports LZCNT instruction
SEP * Supports fast system call instructions
LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode
HLE - Supports Hardware Lock Elision instructions
RTM - Supports Restricted Transactional Memory instructions
DE * Supports I/O breakpoints including CR4.DE
DTES64 * Can write history of 64-bit branch addresses
DS * Implements memory-resident debug buffer
DS-CPL * Supports Debug Store feature with CPL
PCID * Supports PCIDs and settable CR4.PCIDE
INVPCID * Supports INVPCID instruction
PDCM * Supports Performance Capabilities MSR
RDTSCP * Supports RDTSCP instruction
TSC * Supports RDTSC instruction
TSC-DEADLINE * Local APIC supports one-shot deadline timer
TSC-INVARIANT * TSC runs at constant rate
xTPR * Supports disabling task priority messages
EIST * Supports Enhanced Intel Speedstep
ACPI * Implements MSR for power management
TM * Implements thermal monitor circuitry
TM2 * Implements Thermal Monitor 2 control
APIC * Implements software-accessible local APIC
x2APIC * Supports x2APIC
CNXT-ID - L1 data cache mode adaptive or BIOS
MCE * Supports Machine Check, INT18 and CR4.MCE
MCA * Implements Machine Check Architecture
PBE * Supports use of FERR#/PBE# pin
PSN - Implements 96-bit processor serial number
PREFETCHW * Supports PREFETCHW instruction
Maximum implemented CPUID leaves: 0000000F (Basic), 80000008 (Extended).
Logical to Physical Processor Map:
Physical Processor 0 (Hyperthreaded):
**------------------------------------------------------
Physical Processor 1 (Hyperthreaded):
--**----------------------------------------------------
Physical Processor 2 (Hyperthreaded):
----**--------------------------------------------------
Physical Processor 3 (Hyperthreaded):
------**------------------------------------------------
Physical Processor 4 (Hyperthreaded):
--------**----------------------------------------------
Physical Processor 5 (Hyperthreaded):
----------**--------------------------------------------
Physical Processor 6 (Hyperthreaded):
------------**------------------------------------------
Physical Processor 7 (Hyperthreaded):
--------------**----------------------------------------
Physical Processor 8 (Hyperthreaded):
----------------**--------------------------------------
Physical Processor 9 (Hyperthreaded):
------------------**------------------------------------
Physical Processor 10 (Hyperthreaded):
--------------------**----------------------------------
Physical Processor 11 (Hyperthreaded):
----------------------**--------------------------------
Physical Processor 12 (Hyperthreaded):
------------------------**------------------------------
Physical Processor 13 (Hyperthreaded):
--------------------------**----------------------------
Physical Processor 14 (Hyperthreaded):
----------------------------**--------------------------
Physical Processor 15 (Hyperthreaded):
------------------------------**------------------------
Physical Processor 16 (Hyperthreaded):
--------------------------------**----------------------
Physical Processor 17 (Hyperthreaded):
----------------------------------**--------------------
Physical Processor 18 (Hyperthreaded):
------------------------------------**------------------
Physical Processor 19 (Hyperthreaded):
--------------------------------------**----------------
Physical Processor 20 (Hyperthreaded):
----------------------------------------**--------------
Physical Processor 21 (Hyperthreaded):
------------------------------------------**------------
Physical Processor 22 (Hyperthreaded):
--------------------------------------------**----------
Physical Processor 23 (Hyperthreaded):
----------------------------------------------**--------
Physical Processor 24 (Hyperthreaded):
------------------------------------------------**------
Physical Processor 25 (Hyperthreaded):
--------------------------------------------------**----
Physical Processor 26 (Hyperthreaded):
----------------------------------------------------**--
Physical Processor 27 (Hyperthreaded):
------------------------------------------------------**
Logical Processor to Socket Map:
Socket 0:
****************************----------------------------
Socket 1:
----------------------------****************************
Logical Processor to NUMA Node Map:
NUMA Node 0:
****************************----------------------------
NUMA Node 1:
----------------------------****************************
Calculating Cross-NUMA Node Access Cost...
Approximate Cross-NUMA Node Access Cost (relative to fastest):
00 01
00: 1.0 1.1
01: 1.1 1.1
Logical Processor to Cache Map:
Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 0, Level 2, 256 KB, Assoc 8, LineSize 64
**------------------------------------------------------
Unified Cache 1, Level 3, 35 MB, Assoc 20, LineSize 64
****************************----------------------------
Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Unified Cache 2, Level 2, 256 KB, Assoc 8, LineSize 64
--**----------------------------------------------------
Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Unified Cache 3, Level 2, 256 KB, Assoc 8, LineSize 64
----**--------------------------------------------------
Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Unified Cache 4, Level 2, 256 KB, Assoc 8, LineSize 64
------**------------------------------------------------
Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Instruction Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Unified Cache 5, Level 2, 256 KB, Assoc 8, LineSize 64
--------**----------------------------------------------
Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Instruction Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Unified Cache 6, Level 2, 256 KB, Assoc 8, LineSize 64
----------**--------------------------------------------
Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Instruction Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Unified Cache 7, Level 2, 256 KB, Assoc 8, LineSize 64
------------**------------------------------------------
Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Instruction Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Unified Cache 8, Level 2, 256 KB, Assoc 8, LineSize 64
--------------**----------------------------------------
Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Instruction Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Unified Cache 9, Level 2, 256 KB, Assoc 8, LineSize 64
----------------**--------------------------------------
Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Instruction Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Unified Cache 10, Level 2, 256 KB, Assoc 8, LineSize 64
------------------**------------------------------------
Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Instruction Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Unified Cache 11, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------**----------------------------------
Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Instruction Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Unified Cache 12, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------**--------------------------------
Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Instruction Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Unified Cache 13, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------**------------------------------
Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Instruction Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Unified Cache 14, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------**----------------------------
Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Instruction Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 15, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------**--------------------------
Unified Cache 16, Level 3, 35 MB, Assoc 20, LineSize 64
----------------------------****************************
Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Instruction Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Unified Cache 17, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------**------------------------
Data Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Instruction Cache 16, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Unified Cache 18, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------**----------------------
Data Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Instruction Cache 17, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Unified Cache 19, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------**--------------------
Data Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Instruction Cache 18, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Unified Cache 20, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------**------------------
Data Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Instruction Cache 19, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Unified Cache 21, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------**----------------
Data Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Instruction Cache 20, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Unified Cache 22, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------**--------------
Data Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Instruction Cache 21, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Unified Cache 23, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------**------------
Data Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Instruction Cache 22, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Unified Cache 24, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------**----------
Data Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Instruction Cache 23, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Unified Cache 25, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------**--------
Data Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Instruction Cache 24, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Unified Cache 26, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------**------
Data Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Instruction Cache 25, Level 1, 32 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Unified Cache 27, Level 2, 256 KB, Assoc 8, LineSize 64
--------------------------------------------------**----
Data Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Instruction Cache 26, Level 1, 32 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Unified Cache 28, Level 2, 256 KB, Assoc 8, LineSize 64
----------------------------------------------------**--
Data Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Instruction Cache 27, Level 1, 32 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Unified Cache 29, Level 2, 256 KB, Assoc 8, LineSize 64
------------------------------------------------------**
Logical Processor to Group Map:
Group 0:
****************************----------------------------
Group 1:
----------------------------****************************
这是msinfo32命令的转储（有关服务器的信息）：
This is the MsInfo32 command dump (information about the server):
OS Name Microsoft Windows Server 2012 R2 Standard
Version 6.3.9600 Build 9600
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name EMTP6
System Manufacturer HP
System Model ProLiant DL360 Gen9
System Type x64-based PC
System SKU 755258-B21
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU E5-2697 v3 @ 2.60GHz, 2597 Mhz, 14 Core(s), 28 Logical Processor(s)
BIOS Version/Date HP P89, 7/11/2014
SMBIOS Version 2.8
Embedded Controller Version 2.02
BIOS Mode UEFI
Platform Role Enterprise Server
Secure Boot State Off
PCR7 Configuration Not Available
Windows Directory ---removed
System Directory ---removed
Boot Device \Device\HarddiskVolume2
Locale United States
Hardware Abstraction Layer Version = "6.3.9600.17196"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 256 GB
Total Physical Memory 256 GB
Available Physical Memory 246 GB
Total Virtual Memory 294 GB
Available Virtual Memory 283 GB
Page File Space 38.0 GB
Page File ---removed
Hyper-V - VM Monitor Mode Extensions Yes
Hyper-V - Second Level Address Translation Extensions Yes
Hyper-V - Virtualization Enabled in Firmware Yes
Hyper-V - Data Execution Protection Yes
这是任务管理器的屏幕截图和我的程序的结果：
This is the screen shot of TaskManager and my program results:
或者，如果Windows决定启动节点1：
Or, if Windows decided to start it on node 1:
预期的行为：
OS Name Microsoft Windows Server 2008 HPC Edition
Version 6.1.7601 Service Pack 1 Build 7601
Other OS Description Not Available
OS Manufacturer Microsoft Corporation
System Name COMPUTE-13-6
System Manufacturer HP
System Model ProLiant DL160 G6
System Type x64-based PC
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
Processor Intel(R) Xeon(R) CPU X5675 @ 3.07GHz, 3068 Mhz, 6 Core(s), 6 Logical Processor(s)
BIOS Version/Date HP O33, 7/1/2013
SMBIOS Version 2.7
Windows Directory C:\Windows
System Directory C:\Windows\system32
Boot Device \Device\HarddiskVolume1
Locale United States
Hardware Abstraction Layer Version = "6.1.7601.17514"
User Name Not Available
Time Zone Eastern Standard Time
Installed Physical Memory (RAM) 48.0 GB
Total Physical Memory 48.0 GB
Available Physical Memory 40.9 GB
Total Virtual Memory 96.0 GB
Available Virtual Memory 88.4 GB
Page File Space 48.0 GB
Page File C:\pagefile.sys
请注意：我想我们通过改变固定的问题，在BIOS中交叉存取内存参数。但我给了我们奇怪的结果。据微软的Technet 我们折戟BIOS设置为NON -Interleaved记忆**（这是由OS才能看到将系统作为NUMA）。
Note: I thought we fixed the problem by changing "Interleaved Memory" parameter in the bios. But i gives us weird results. According to Microsoft Technet we set back the BIOS setting to "NON-Interleaved memory"** (which is required by the OS to see the system as NUMA).
推荐答案
该错误已固定由一个新的（尚未公布） HP的Bios （当时。写这部分内容）
The bug has been fixed by a new (yet unpublished) HP Bios (at the time of writing this).
新的BIOS（针对惠普的Proliant DL360和DL380 Gen9）引入一个新的设置：NUMA组大小优化与[集群的选择 - 默认]或[平]。惠普称，将其设置为持平。
The new Bios (targeting HP Proliant DL360 and DL380 Gen9) introduce a new setting: "NUMA Group Size Optimization" with choice of [Clustered - default] or [Flat]. HP says to set it to flat.
这答案的sceenshot部分已在DL380而不是因为服务器的可用性DL360进行。但我希望在DL360相同的行为。问题disapeared，我们只有一个组。
The sceenshot part of this answer has been conducted on a DL380 instead of a DL360 because of server availability. But I expect same behavior on DL360. The problem disapeared, we had only one group.
据我所知，操作系统与BIOS知道CPU（S）配置通信。在BIOS起到在OS将如何呈现可用于应用程序（处理器组，亲和，等等）的逻辑处理器中起重要作用。
As far as I know, the OS communicate with the BIOS to know the CPU(s) configuration. The Bios play an important role in how the OS will present the logical processors available to applications (Processor Group, Affinity, etc).
关于Microsoft文档Supporting系统具有超过64个处理器并的Processor组它明确指出多个处理器组会当逻辑处理器（LC）计数> 64只被创建。在我们的服务器（56 LC）与NUMA架构设置为集群，我们有2个处理器组。硬件工程师在惠普的Bios开发团队的工作解释我，当设置为群集时，BIOS是由填充逻辑处理器的实数到72的逻辑处理器（为的E5 V3系列）。 LC的实数是我们DL360 56。这就是为什么我们增加2组，而不是1，微软的文档似乎准确的原因。我个人认为，这将是最好创建每个NUMA节点尽可能但是在我们的情况下1组，有一个bug。什么是错误的，很难惠普或微软之间知道何时惠普的Bios设置为群集（默认值），但微软似乎并不支持该选项，这似乎引起我们的问题。
About the Microsoft documentation Supporting Systems That Have More Than 64 Processors and Processor Groups it is clearly stated that more than one processor group will only be created when the Logical Processor (LC) count is >64. On our server (56 LC) with Numa Architecture set to "Clustered" we had 2 processor groups. A hardware engineer working at HP Bios dev team explained me that when set to "Clustered", the Bios is fooling Windows by padding the real number of logical processor to 72 Logical Processor (the max number of Logical Processor for the E5 v3 Family). The real number of LC is 56 in our DL360. That's the reason why we add 2 groups instead of 1. The Microsoft documentation seems accurate. I personally think that it would be better to create 1 group per numa node whenever possible but in our case, there is a bug. What is faulty is hard to know between HP or Microsoft when the HP Bios setting is set to Clustered (default) but Microsoft seems to not support that option which seems to cause our problem.
在HP BIOS的DL360和DL380，BIOS配置沼配置设置为集群（默认）将创建2组虽然只有56逻辑处理器（超线程时）。其结果是，只有一个处理器是在时间的任何应用程序是可见的。大概也是因为惠普通过浸轧逻辑处理器的假数字愚弄的Windows。这听起来像微软没有想到。我们的C＃应用程序不能在2组运行。很难指责这种行为微软在HP做的东西，他们无法预料。 Perhaps we will see, one day, Windows supporting many groups when LC <= 64.
On HP Bios for DL360 and DL380, The Bios configuration "Numa Configuration" set to "Clustered" (default) will create 2 groups although there is only 56 Logical Processors (when hyperthreaded). The result is that only one processor is visible at a time for any application. Probably also due to HP fooling Windows by padding fake number of Logical Processors. It sounds like Microsoft does not expect that. Our C# app can't run on the 2 groups. It's hard to blame Microsoft on that behavior where HP does something they can't anticipated. Perhaps we will see, one day, Windows supporting many groups when LC <= 64.
About Prime95. This CPU stress test software has good documentation on Wikipedia that clearly state that it will load into only one processor group (in Limits section).
About Prime95. This CPU stress test software has good documentation on Wikipedia that clearly state that it will load into only one processor group (in Limits section).
这篇关于无法在C＃应用程序使用多个处理器组对我的线程的文章就介绍到这了，希望我们推荐的答案对大家有所帮助，也希望大家多多支持IT屋！
